PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 451

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

28.2
PIC18F47J53 family devices have both a conventional
WDT circuit and a dedicated, Deep Sleep capable
Watchdog Timer. When enabled, the conventional
WDT operates in normal Run, Idle and Sleep modes.
This data sheet section describes the conventional
WDT circuit.
The dedicated, Deep Sleep capable WDT can only be
enabled in Deep Sleep mode. This timer is described in
Section 4.6.4
(DSWDT)”.
The conventional WDT is driven by the INTRC oscilla-
tor. When the WDT is enabled, the clock source is also
enabled. The nominal WDT period is 4 ms and has the
same stability as the INTRC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by the WDTPS bits
in Configuration Register 2H. Available periods range
from about 4 ms to 135 seconds (2.25 minutes
depending
postscaler). The WDT and postscaler are cleared
FIGURE 28-1:
 2010 Microchip Technology Inc.
All Device Resets
INTRC Oscillator
WDTPS<3:0>
Watchdog Timer (WDT)
SWDTEN
on
CLRWDT
Sleep
“Deep
voltage,
WDT BLOCK DIAGRAM
Sleep
temperature
Enable WDT
Watchdog
WDT Counter
128
and
INTRC Control
4
Timer
WDT
Preliminary
Programmable Postscaler
1:1 to 1:32,768
PIC18F47J53 FAMILY
whenever a SLEEP or CLRWDT instruction is executed,
or a clock failure (primary or Timer1 oscillator) has
occurred.
28.2.1
The WDTCON register (Register 28-11) is a readable
and writable register. The SWDTEN bit enables or dis-
ables WDT operation. This allows software to override
the WDTEN Configuration bit and enable the WDT only
if it has been disabled by the Configuration bit.
LVDSTAT is a read-only status bit that is continuously
updated and provides information about the current
level of V
voltage regulator is enabled.
Note 1: The CLRWDT and SLEEP instructions
2: When a CLRWDT instruction is executed,
DDCORE
WDT
CONTROL REGISTER
clear the WDT and postscaler counts
when executed.
the postscaler count will be cleared.
Reset
. This bit is only valid when the on-chip
DS39964B-page 451
Wake-up from
Power-Managed
Modes
WDT
Reset