PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 154

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F47J53 FAMILY
TABLE 10-7:
TABLE 10-8:
DS39964B-page 154
RC6/CCP9/
PMA5/TX1/
CK1/RP17
RC7/CCP10/
PMA4/RX1/
DT1/SDO1/
RP18
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
Note 1:
PORTC
LATC
TRISC
ANCON1
CM2CON
UCON
UCFG
RTCCFG
Name
Pin
2:
input/output; I
is overridden for this option)
Enhanced PWM output is available only on PIC18F4XJ53 devices.
This bit is only available on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and
PIC18LF47J53).
PORTC I/O SUMMARY
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
TRISC7
VBGEN
RTCEN
UTEYE
Function
LATC7
PMA5
PMA4
Bit 7
CON
CCP10
RC7
SDO1
CCP9
RP17
RP18
—
RC6
CK1
RC7
RX1
TX1
DT1
2
(2)
(2)
C/SMB = I
UOEMON
PPBRST
TRISC6
Setting
LATC6
Bit 6
COE
TRIS
RC6
—
—
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
x
1
1
0
0
1
0
2
C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or
RTCWREN RTCSYNC HALFSEC
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
1
I
I
I
I
I
I
I
I
I
(1)
CPOL
Bit 5
RC5
SE0
—
—
—
—
(CONTINUED)
ST/TTL/
ST/TTL Parallel Master Port io_addr_in<5>.
Type
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
Preliminary
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
PCFG12
EVPOL1
PKTDIS
UPUEN
PORTC<6> data input.
LATC<6> data output.
Capture input.
Compare/PWM output.
Parallel Master Port address.
Asynchronous serial transmit data output (EUSART
module); takes priority over port data. User must configure
as an output.
Synchronous serial clock input (EUSART module).
Synchronous serial clock output (EUSART module); takes
priority over port data.
Remappable Peripheral Pin 17 input.
Remappable Peripheral Pin 17 output.
PORTC<7> data input.
LATC<7> data output.
Capture input.
Compare/PWM output.
Parallel Master Port address.
Asynchronous serial receive data input (EUSART module).
Synchronous serial data input (EUSART module). User
must configure as an input.
Synchronous serial data output (EUSART module); takes
priority over port data.
SPI data output (MSSP1 module).
Remappable Peripheral Pin 18 input.
Remappable Peripheral Pin 18 output.
Bit 4
RC4
—
—
EVPOL0
PCFG11
UTRDIS
USBEN
Bit 3
—
—
—
RESUME
Description
PCFG10
TRISC2
RTCOE
LATC2
CREF
FSEN
Bit 2
RC2
 2010 Microchip Technology Inc.
RTCPTR1 RTCPTR0
SUSPND
TRISC1
PCFG9
LATC1
CCH1
PPB1
Bit 1
RC1
TRISC0
PCFG8
LATC0
CCH0
PPB0
Bit 0
RC0
—