PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 56

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

continue to maintain their previous states, even after the
configured as outputs will continue to drive their previous
PIC18F47J53 FAMILY
4.6.2
During Deep Sleep, the general purpose I/O pins will
retain their previous states.
Pins that are configured as inputs (TRIS bit set) prior to
entry into Deep Sleep will remain high-impedance
during Deep Sleep.
Pins that are configured as outputs (TRIS bit clear)
prior to entry into Deep Sleep will remain as output pins
during Deep Sleep. While in this mode, they will drive
the output level determined by their corresponding LAT
bit at the time of entry into Deep Sleep.
When the device wakes back up, the I/O pin behavior
depends on the type of wake up source.
If the device wakes back up by an RTCC alarm, INT0
interrupt, DSWDT or ULPWU event, all I/O pins will
device has finished the POR sequence and is executing
application code again. Pins configured as inputs during
Deep Sleep will remain high-impedance, and pins
value.
After waking up, the TRIS and LAT registers will be
reset, but the I/O pins will still maintain their previous
states. If firmware modifies the TRIS and LAT values
for the I/O pins, they will not immediately go to the
newly configured states. Once the firmware clears the
RELEASE bit (DSCONL<0>), the I/O pins will be
“released”. This causes the I/O pins to take the states
configured by their respective TRIS and LAT bit values.
If the Deep Sleep BOR (DSBOR) circuit is enabled, and
V
olds, the I/O pins will be immediately released similar to
clearing the RELEASE bit. All previous state informa-
tion will be lost, including the general purpose DSGPR0
and DSGPR1 contents. See Section 4.6.5 “Deep
Sleep Brown-Out Reset (DSBOR)” for additional
details regarding this scenario
If a MCLR Reset event occurs during Deep Sleep, the
I/O pins will also be released automatically, but in this
case, the DSGPR0 and DSGPR1 contents will remain
valid.
In all other Deep Sleep wake-up cases, application
firmware needs to clear the RELEASE bit in order to
reconfigure the I/O pins.
DS39964B-page 56
DD
drops below the DSBOR and V
I/O PINS DURING DEEP SLEEP
DD
rail POR thresh-
Preliminary
registers. If the wake-up source asserts prior to entering
4.6.3
The device can be awakened from Deep Sleep mode by
a MCLR, POR, RTCC, INT0 I/O pin interrupt, DSWDT or
ULPWU event. After waking, the device performs a
POR. When the device is released from Reset, code
execution will begin at the device’s Reset vector.
The software can determine if the wake-up was caused
from an exit from Deep Sleep mode by reading the DS
bit (WDTCON<3>). If this bit is set, the POR was
caused by a Deep Sleep exit. The DS bit must be
manually cleared by the software.
The software can determine the wake event source by
reading the DSWAKEH and DSWAKEL registers.
When the application firmware is done using the
DSWAKEH and DSWAKEL status registers, individual
bits do not need to be manually cleared before entering
Deep Sleep again. When entering Deep Sleep mode,
these registers are automatically cleared.
4.6.3.1
Deep Sleep wake-up events are only monitored while
the processor is fully in Deep Sleep mode. If a wake-up
event occurs before Deep Sleep mode is entered, the
event status will not be reflected in the DSWAKE
Deep Sleep, the CPU will either go to the interrupt vector
(if the wake source has an interrupt bit and the interrupt
is fully enabled) or will abort the Deep Sleep entry
sequence by executing past the SLEEP instruction if the
interrupt was not enabled. In this case, a wake-up event
handler should be placed after the SLEEP instruction to
process the event and re-attempt entry into Deep Sleep
if desired.
When the device is in Deep Sleep with more than one
wake-up source simultaneously enabled, only the first
wake-up source to assert will be detected and logged
in the DSWAKEH/DSWAKEL status registers.
4.6.4
Deep Sleep has its own dedicated WDT (DSWDT) with
a postscaler for time-outs of 2.1 ms to 25.7 days,
configurable through the bits, DSWDTPS<3:0>.
The DSWDT can be clocked from either the INTRC or
the T1OSC/T1CKI input. If the T1OSC/T1CKI source
will be used with a crystal, the T1OSCEN bit in the
T1CON register needs to be set prior to entering Deep
Sleep. The reference clock source is configured through
the DSWDTOSC bit.
DSWDT is enabled through the DSWDTEN bit. Entering
Deep Sleep mode automatically clears the DSWDT. See
Section 28.0 “Special Features of the CPU” for more
information.
DEEP SLEEP WAKE-UP SOURCES
DEEP SLEEP WATCHDOG TIMER
(DSWDT)
Wake-up Event Considerations
 2010 Microchip Technology Inc.