PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 378

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F47J53 FAMILY
22.8
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed
mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT<2:0> and
ADCS<2:0> bits in ADCON1 should be updated in
accordance with the power-managed mode clock that
will be used. After the power-managed mode is entered
(either of the power-managed Run modes), an A/D
acquisition or conversion may be started. Once an
acquisition or conversion is started, the device should
continue to be clocked by the same power-managed
EXAMPLE 22-1:
TABLE 22-2:
DS39964B-page 378
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
ADCTRIG
ADRESH
ADRESL
ADCON0
ANCON0
ADCON1
ANCON1
CCP2CON
PORTA
TRISA
Legend:
Note 1:
CALIBRATION
Name
Operation in Power-Managed
Modes
BCF
BSF
BSF
BSF
BTFSC
BRA
BCF
These bits are only available on 44-pin devices.
— = unimplemented, read as ‘0’, r = reserved. Shaded cells are not used for A/D conversion.
A/D Result Register High Byte
A/D Result Register Low Byte
GIE/GIEH
PCFG7
PMPIF
PMPIE
PMPIP
OSCFIF
OSCFIE
OSCFIP
SUMMARY OF A/D REGISTERS
VBGEN
TRISA7
VCFG1
ADFM
P2M1
Bit 7
ANCON0,PCFG0
ADCON0,ADON
ADCON1,ADCAL
ADCON0,GO
ADCON0,GO
CALIBRATION
ADCON1,ADCAL
RA7
—
SAMPLE A/D CALIBRATION ROUTINE
(1)
(1)
(1)
(1)
PEIE/GIEL
PCFG6
TRISA6
VCFG0
ADCAL
CM2IF
CM2IE
CM2IP
P2M0
ADIE
ADIP
Bit 6
ADIF
RA6
—
r
(1)
;Make Channel 0 analog
;Enable A/D module
;Enable Calibration
;Start a dummy A/D conversion
;
;Wait for the dummy conversion to finish
;
;Calibration done, turn off calibration enable
;Proceed with the actual A/D conversion
PCFG5
TMR0IE
TRISA5
ACQT2
DC2B1
CM1IF
CM1IE
CM1IP
RC1IF
RC1IE
RC1IP
CHS3
Bit 5
RA5
—
—
(1)
Preliminary
PCFG12
PCFG4
ACQT1
INT0IE
DC2B0
USBIE
USBIP
USBIF
TX1IF
TX1IE
TX1IP
CHS3
Bit 4
—
—
—
mode clock source until the conversion has been com-
pleted. If desired, the device may be placed into the
corresponding power-managed Idle mode during the
conversion.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in the Sleep mode requires the A/D RC clock
to be selected. If bits, ACQT<2:0>, are set to ‘000’ and
a conversion is started, the conversion will be delayed
one instruction cycle to allow execution of the SLEEP
instruction and entry to Sleep mode. The IDLEN and
SCS bits in the OSCCON register must have already
been cleared prior to starting the conversion.
CCP2M3
PCFG11
SSP1IE
SSP1IP
TRISA3
SSP1IF
BCL1IF
BCL1IE
BCL1IP
PCFG3
ACQT0
CHS1
RBIE
Bit 3
RA3
—
CCP2M2
PCFG10
TMR0IF
CCP1IE
CCP1IP
CCP1IF
HLVDIF
HLVDIE
HLVDIP
TRISA2
PCFG2
ADCS2
CHS0
Bit 2
RA2
—
 2010 Microchip Technology Inc.
TRIGSEL1 TRIGSEL0
GO/DONE
CCP2M1
TMR2IE
TMR2IP
TMR3IE
TMR3IP
TMR2IF
TMR3IF
TRISA1
PCFG1
ADCS1
PCFG9
INT0IF
Bit 1
RA1
CCP2M0
TMR1IE
TMR1IP
TMR1IF
CCP2IF
CCP2IE
CCP2IP
TRISA0
PCFG0
ADCS0
PCFG8
ADON
Bit 0
RBIF
RA0