PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 394

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F47J53 FAMILY
23.5
The USB module can generate multiple interrupt con-
ditions. To accommodate all of these interrupt sources,
the module is provided with its own interrupt logic
structure, similar to that of the microcontroller. USB
interrupts are enabled with one set of control registers
and trapped with a separate set of flag registers. All
sources are funneled into a single USB interrupt
request, USBIF (PIR2<4>), in the microcontroller’s
interrupt logic.
FIGURE 23-7:
FIGURE 23-8:
DS39964B-page 394
Note 1:
Differential Data
USB Interrupts
The control transfer shown here is only an example showing events that can occur for every transaction. Typical
control transfers will spread across multiple frames.
USB Reset
URSTIF
RESET
UEIR (Flag) and UEIE (Enable) Registers
CRC5EE
CRC5EF
Start-of-Frame (SOF)
BTOEE
BTOEF
BTSEF
BTSEE
Second Level USB Interrupts
PIDEE
PIDEF
CRC16EE
CRC16EF
USB INTERRUPT LOGIC FUNNEL
EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS
DFN8EF
DFN8EE
(USB Error Conditions)
SOFIF
SOF
SETUP
DATA
Preliminary
STATUS
Figure 23-7 provides the interrupt logic for the USB
module. There are two layers of interrupt registers in
the USB module. The top level consists of overall USB
status interrupts; these are enabled and flagged in the
UIE and UIR registers, respectively. The second level
consists of USB error conditions, which are enabled
and flagged in the UEIR and UEIE registers. An
interrupt condition in any of these triggers a USB Error
Interrupt Flag (UERRIF) in the top level.
Interrupts may be used to trap routine events in a USB
transaction. Figure 23-8 provides some common
events within a USB frame and its corresponding
interrupts.
SETUP Token
STALLIF
STALLIE
UERRIE
UERRIF
ACTVIE
URSTIE
OUT Token
ACTVIF
URSTIF
Control Transfer
From Host
From Host
From Host
IN Token
IDLEIF
IDLEIE
SOFIE
TRNIE
SOFIF
TRNIF
UIR (Flag) and UIE (Enable) Registers
Top Level USB Interrupts
(USB Status Interrupts)
Empty Data
Transaction
From Host
From Host
To Host
(1)
Data
Data
 2010 Microchip Technology Inc.
From Host
To Host
To Host
ACK
ACK
ACK
SOF
1 ms Frame
USBIF
Transaction
Set TRNIF
Set TRNIF
Set TRNIF
Complete