PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 338

• Manufacturer Part Number: PIC18F27J53T-I/SO
• Description: 28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F47J53 FAMILY
20.5.12
An Acknowledge sequence is enabled by setting the
Acknowledge
(SSPxCON2<4>). When this bit is set, the SCLx pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDAx pin. If the user wishes to
generate an Acknowledge, then the ACKDT bit should
be cleared. If not, the user should set the ACKDT bit
before starting an Acknowledge sequence. The BRG
then counts for one rollover period (T
pin is deasserted (pulled high). When the SCLx pin is
sampled high (clock arbitration), the BRG counts for
T
ACKEN bit is automatically cleared, the BRG is turned
off and the MSSP module then goes into an inactive
state (Figure 20-25).
20.5.12.1
If the user writes the SSPxBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write does
not occur).
FIGURE 20-25:
FIGURE 20-26:
DS39964B-page 338
BRG
Note:
Note:
; the SCLx pin is then pulled low. Following this, the
ACKNOWLEDGE SEQUENCE
TIMING
WCOL Status Flag
SCLx
SDAx
T
T
BRG
BRG
Sequence
Write to SSPxCON2,
SSPxIF
SDAx
SCLx
Falling edge of
9th clock
= one Baud Rate Generator period.
= one Baud Rate Generator period.
ACKNOWLEDGE SEQUENCE WAVEFORM
STOP CONDITION RECEIVE OR TRANSMIT MODE
Acknowledge sequence starts here,
ACK
SSPxIF set at
the end of receive
set PEN
Enable
ACKEN = 1, ACKDT = 0
write to SSPxCON2,
BRG
T
) and the SCLx
T
bit,
BRG
BRG
SDAx asserted low before rising edge of clock
to set up Stop condition
8
D0
ACKEN
T
SCLx brought high after T
BRG
Preliminary
Cleared in
software
P
T
BRG
SCLx = 1 for T
after SDAx sampled high. P bit (SSPxSTAT<4>) is set
T
BRG
ACK
20.5.13
A Stop bit is asserted on the SDAx pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPxCON2<2>). At the end of a
receive/transmit, the SCLx line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDAx line low. When the
SDAx line is sampled low, the BRG is reloaded and
counts down to 0. When the BRG times out, the SCLx
pin will be brought high and one Baud Rate Generator
rollover count (T
deasserted. When the SDAx pin is sampled high while
SCLx is high, the Stop bit (SSPxSTAT<4>) is set. A
T
set (Figure 20-26).
20.5.13.1
If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write does
not occur).
BRG
PEN bit (SSPxCON2<2>) is cleared by
T
BRG
hardware and the SSPxIF bit is set
later, the PEN bit is cleared and the SSPxIF bit is
9
BRG
SSPxIF set at the end
of Acknowledge sequence
BRG
, followed by SDAx = 1 for T
STOP CONDITION TIMING
WCOL Status Flag
ACKEN automatically cleared
BRG
) later, the SDAx pin will be
 2010 Microchip Technology Inc.
Cleared in
software
BRG