cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 109

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cx28250

Manufacturer Part Number
cx28250
Description
Cx28250 Atm Physical Interface Phy Devices
Manufacturer
Mindspeed Technologies
Datasheet

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CX28250
ATM Physical Interface (PHY) Devices
Table 4-9. Counters
28250-DSH-002-C
NOTE(S):
(1)
(2)
Address
These bits are cleared automatically by internal circuitry after the indicated error insertion has taken place. Clearing takes
precedence over a simultaneous write operation to this register.
Enabled by setting EnCntrLat in General Control register (0x00), bit 4 to a logic 1.
0x4C
0x4D
0x4E
0x50
0x51
0x52
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5C
0x5D
0x5E
0x60
0x61
0x62
0x64
0x65
0x66
0x4F
0x5F
CORRCNT
NONCNTH
LOCDCNT
NONCNTL
RXCNTM
UNCCNT
B2CNTM
TXCNTM
RXCNTH
OOFCNT
B2CNTH
B1CNTH
B3CNTH
LFCNTM
PFCNTH
TXCNTH
RXCNTL
B2CNTL
B1CNTL
B3CNTL
LFCNTH
PFCNTL
TXCNTL
LFCNTL
Name
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Mindspeed Technologies
Latching
OneSec
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
LOCD Event Counter
Corrected HEC Error Counter
Uncorrected HEC Error Counter
OOF Event Counter
Line BIP Error Counter (low byte)
Line BIP Error Counter (mid byte)
Line BIP Error Counter (high byte)
Section BIP Error Counter (low byte)
Section BIP Error Counter (high byte)
Path BIP Error Counter (low byte)
Path BIP Error Counter (high byte)
Line REI Error Counter (low byte)
Line REI Error Counter (mid byte)
Line REI Error Counter (high byte)
Path REI Error Counter (low byte)
Path REI Error Counter (high byte)
Non-Matching Cell Counter (low byte)
Non-Matching Cell Counter (high byte)
Transmitted Cell Counter (low byte)
Transmitted Cell Counter (mid byte)
Transmitted Cell Counter (high byte)
Received Cell Counter (low byte)
Received Cell Counter (mid byte)
Received Cell Counter (high byte)
Description
4.0 Registers
Number
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