cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 128

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

4.0 Registers
4.1 Registers
0x05—IDLPAY (Transmit Idle Cell Payload Control Register)
The IDLPAY register contains the transmit idle cell payload.
0x72—INLK (In Lock Coefficient Register)
The value in this register configures the PLL.
0x5A—LFCNTH (Line REI Error Counter [High Byte])
The LFCNTH counter tracks the number of Line REI errors.
4-30
7–0
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0x15 (-26)
0x40 (-23)
Default
Default
Default
0
0
0
0
0
0
x
x
0
1
1
0
1
0
1
0
LFCnt[17]
LFCnt[16]
IdlPay[7]
IdlPay[6]
IdlPay[5]
IdlPay[4]
IdlPay[3]
IdlPay[2]
IdlPay[1]
IdlPay[0]
Name
Name
Name
—
—
—
—
—
—
—
Reserved, set to 0.
Reserved, set to 0.
Reserved, set to 0.
Reserved, set to 0.
Reserved, set to 0.
Reserved, set to 0.
Line REI Error counter bit 17 (MSB).
Line REI Error counter bit 16.
These bits hold the Transmit Idle Cell Payload values for outgoing idle cells.
Sets the window threshold for the Phase Lock Loop once the loop has acquired lock.
This register should be reprogrammed to 0x15 in the -23 version.
Mindspeed Technologies
Description
Description
Description
™
ATM Physical Interface (PHY) Devices
28250-DSH-002-C
CX28250