cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 118

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

4.0 Registers
4.1 Registers
0x4D—CORRCNT (Corrected HEC Error Counter)
The CORRCNT counter tracks the number of corrected HEC errors.
0x08—CVAL (Cell Validation Control Register)
The CVAL register controls the validation of incoming cells to be received across the UTOPIA interface.
4-20
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
x
x
x
x
x
x
x
x
0
1
1
1
0
0
0
0
EnRxCellScr
DisCellRcvr
CorrCnt[7]
CorrCnt[6]
CorrCnt[5]
CorrCnt[4]
CorrCnt[3]
CorrCnt[2]
CorrCnt[1]
CorrCnt[0]
DisHECChk
EnHdrCorr
EnRxCos
DisLOCD
Name
RejHdr
DelIdle
Name
Corrected HEC Error counter bit 7 (MSB).
Corrected HEC Error counter bit 6.
Corrected HEC Error counter bit 5.
Corrected HEC Error counter bit 4.
Corrected HEC Error counter bit 3.
Corrected HEC Error counter bit 2.
Corrected HEC Error counter bit 1.
Corrected HEC Error counter bit 0 (LSB).
When written to a logic 1, this bit enables the Reject Header function. When enabled,
cells with matching headers are rejected and all others are accepted. When written to
0, cells with headers matching the RXHDRx/RXMSKx definition are accepted.
When written to a logic 1, this bit enables the Deletion of Idle Cells. When enabled,
cells matching the RXIDL/IDLMSK definition are deleted from the received cell stream.
When written to 0, idle cells are included in the received stream.
When written to a logic 1, this bit enables the x
When written to a logic 1, this bit enables the Receiver HEC Coset.
When written to a logic 1, this bit enables the HEC Correction state machine. When
written to 0, only HEC error detection is performed.
When written to a logic 1, this bit disables HEC Checking. When disabled, HEC
checking is not performed as a cell validation criteria.
When written to a logic 1, this bit disables the Cell Receiver. When disabled, all cell
reception is disabled on the next cell boundary. When written to 0, cell reception
begins or resumes on the next cell boundary. (See also UtopDis (bit 5) in the
0x0B–UTOP2 register, on page 4-25.)
When written to a logic 1, this bit disables Loss of Cell Delineation. When disabled,
cells are passed to the UTOPIA port even if cell delineation has not been found. When
written to 0, cells are passed to the UTOPIA port only while cell alignment has been
achieved.
Mindspeed Technologies
Description
Description
™
ATM Physical Interface (PHY) Devices
43
+1 Cell Scrambler in the cell receiver.
28250-DSH-002-C
CX28250