cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 45
cx28250
Manufacturer Part Number
cx28250
Description
Cx28250 Atm Physical Interface Phy Devices
Manufacturer
Mindspeed Technologies
Datasheet
1.CX28250.pdf
(213 pages)
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CX28250
ATM Physical Interface (PHY) Devices
2.2.1 Loss of Lock
28250-DSH-002-C
Loss of Lock (LOL) status indicates that the receive PLL has lost
synchronization. When LOL occurs, bit 6 of the SECINT register (0x3D) is
asserted if it has been enabled by bit 6 of the ENSEC register (0x35). LOL also
appears in bit 6 of the RXSEC register (0x45).
registers ENLFOUT and ENPFOUT.
to the transmit and receive clocks.
automatically derive this output from the LPLLClk input until the recovered clock
is available. On older versions, (such as the -23), this output is shut off during
LOS and LOF conditions.
LOL can also be enabled to appear on LFout and PFout outputs via the
The CX28250 provides the following two clock outputs that are phase locked
• TxFrameRef: This is an 8 KHz or 19.44 MHz reference derived from the
• RxFrameRef: The output of this pin is either an 8 KHz or 19.44 MHz
During a LOS condition the newest versions of the CX28250, (-26 and above),
transmit clock. Its frequency and polarity are controlled by bits 0 and 1 in
the TXSEC register.
reference derived from the recovered clock. Its frequency and polarity are
controlled by bits 0 and 1 in the RXSEC register.
Mindspeed Technologies
™
2.0 Functional Description
2.2 Clock Circuits
2-9
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