cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 51

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

CX28250
ATM Physical Interface (PHY) Devices
28250-DSH-002-C
Data Link Transmit
Data Link Receive
The CX28250 can insert data into the D1–D12 octets of the outgoing data stream.
This function is controlled by EnTxSecDL, bit 6 of the TXSEC, 0x0C register
and EnTxLinDL, bit 4 of the TXLIN, 0x0D register. When EnTxSecDL is set to
1, serial data input on the DLTxData pin is inserted into the D1, D2, and D3
octets. Likewise, setting EnTxLinDL to 1 results in the serial data from the
DLTxData pin being inserted in the D4 through D12 octets of the outgoing
stream. The CX28250 indicates that it is ready for D1, D2, and D3 octets by
outputting a logic high on the statout[3] pin; it outputs a logic low when D4-D12
data is expected. If either EnTxSecDL or EnTxLinDL is set, the corresponding
octets will be filled with 0x00.
or EnTxLinDL are set.
(both idle and data cells), synchronized to the UTOPIA transmit side. This is
provided for SAR scheduling activities.
Serial data provided on DLTxData when this pin is high is transmitted in octets
D1, D2, and D3. When this line is low, data from the DLTxData pin is inserted
into octets D4 through D12.
Access to incoming octets D1–D12 is provided via the StatOut[5], StatOut[6],
and StatOut[7] pins. This function is controlled by bits 0 and 1 of the RXLIN,
0x46, register as shown on page 45. When either of these bits is set high, the
StatOut pins are defined as follows:
Incoming octets D1, D2, and D3 are output serially on StatOut[6] pin when this
output is high. When this line is low, data from octets D4 through D12 are output
serially on StatOut [6] pin.
synchronized to the clock on StatOut[7].
synchronized with StatOut [6].
StatOut [2], StatOut [3] and StatOut [4] are redefined whenever EnTxSecDL
StatOut [2]: This pin outputs a pulse at the beginning of every cell slot time,
StatOut [3]: This becomes the transmit Data Link indicator, TxDLI, output.
StatOut [4]: The transmit clock for DL data is output on this pin.
StatOut[5]: This becomes the Receive Data Link indicator, RxDLI, output.
StatOut [6]: This pin outputs the incoming data in a serial bit stream
StatOut [7]: This output is the serial data clock for incoming data and is
Refer to
Mindspeed Technologies
Section 5.1.6
for the Data Link timing.
2.3 SONET/SDH Framer and Overhead Processor
™
2.0 Functional Description
2-15