cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 84

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

2.0 Functional Description
2.7 Loopback Modes
2.7.1 Line Loopback
Figure 2-15. Near-end Line Loopback Diagram
2-48
LTxClkO+/-
LTxData+/-
PECL Logic
LRxData+/-
ATM WIRE
LTxClkI+/-
LRxClk+/-
Interface
SigDet
Level
(19.44 MHz)
PLLCLK
TCK
Line Interface
Interface
Controller
Transmit
TRST*
and Clock
Recovery
Line
JTAG
Receive
8kHzIn
Loopback
Control
TMS
TDI
TDO
TxDL
2.7 Loopback Modes
Loopbacks are diagnostic tools that verify the data path. The CX28250 has three
loopback modes: Line Loopback and UTOPIA Loopback, which check the line
between a remote device and the PHY, and Source Loopback, which checks that
the host (the ATM layer) is communicating with the PHY. Line Loopback is
illustrated in
Source Loopback is illustrated in
Line loopback is enabled or disabled by bit 1 of the CLKREC register (0x01).
When Line Loopback is enabled, all incoming data on the Receive Line Interface
is retransmitted out the Transmit Line Interface. The received data is also passed
through the PHY’s normal path to be output on the UTOPIA interface.
data is output on the UTOPIA bus. However, the receive PECL inputs are directly
connected to the Transmit PECL outputs and the internal transmit block is
disabled. Thus, there is no processing performed in the transmit direction. The
CX28250 simply retransmits whatever signal is received.
Tx Overhead
Rx Overhead
SONET Line Framer
In this mode, the incoming signal is processed by the receive block and the
Extract
Insert
Transmit Framer
Receive Framer
STS-3c/STM-1
STS-3c/STM-1
Mindspeed Technologies
Figure
StatOut[0:7]
Status
InsPthAIS
2-15, UTOPIA Loopback is illustrated in
ATM Cell Framer
InsLnAIS
Performance Monitoring
Receive Cell
MRdy
Alignment
Interrupt Control
Cell Counters
OneSecIn
Figure
Generation
Clock and
OneSecOut
Tx Cell
Control
MInt*
™
2-17.
RxFrameRef
Rx VPI/VCI
Screening
Validation
ATM Physical Interface (PHY) Devices
MAddr[6:0]
Rx Cell
TxFrameRef
Microprocessor
MData[7:0]
Interface
PFOut
Interface
Interface
Transmit
UTOPIA
Receive
UTOPIA
Level 2
Level 2
4-cell
4-cell
FIFO
FIFO
Control Lines
Host
Host
Figure
28250-DSH-002-C
LFOut
2-16, and
Interface
UTOPIA
Level 2
UTxClk
UTxClAv
UTxEnb*
UTxSOC
UTxData[15:0]
TxPrty
UTxAddr[4:0]
URxClk
URxClAv
URxEnb*
URxSOC
URxData[15:0]
URxPrty
URxAddr[4:0]
CX28250
500035_018