cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 122

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

4.0 Registers
4.1 Registers
0x37—ENPTH (Receive Path Interrupt Mask Control Register)
The ENPTH register controls which of the interrupts listed in the PthInt register (0x3F) appear on the MInt*
pin, provided that EnPthInt (bit 5) in the ENSUMINT register (0x34) is enabled, and EnIntPin (bit 6) in the
GEN register (0x00) is enabled.
0x35—ENSEC (Receive Section Interrupt Mask Control Register)
The ENSEC register controls which of the interrupts listed in the SecInt register (0x3D) appear on the MInt*
pin, provided that EnSecInt (bit 7) in the ENSUMINT register (0x34) is enabled, and EnIntPin (bit 6) in the
GEN register (0x00) is enabled.
4-24
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
EnhanceRDI (-23) When written to a logic 1, this bit enables the Enhanced RDI function. When written
EnSecTrace
EnSigDet
DisRxScr
EnB1Err
EnLOS
EnOOF
Name
EnLOL
EnLOF
EnPthTrace
EnUneq-P
EnPLM-P
EnRDI-P
EnAIS-P
EnB3Err
EnREI-P
— (-26)
Name
When written to a logic 1, this bit enables the Signal Detect Interrupt.
When written to a logic 1, this bit enables the Loss of Lock Interrupt.
When written to a logic 1, this bit enables the Loss of Signal Interrupt.
When written to a logic 1, this bit enables the Out of Frame Interrupt.
When written to a logic 1, this bit enables the Loss of Frame Interrupt.
When written to a logic 1, this bit enables the Section BIP Error Interrupt.
When written to a logic 1, this bit enables the Section Trace Interrupt.
When written to a logic 1, this bit disables the Receive Frame Scrambler. When written to 0,
scrambling is enabled.
When written to a logic 1, this bit enables the AIS-P Interrupt.
When written to a logic 1, this bit enables the RDI-P Interrupt.
When written to a logic 1, this bit enables the B3 Error Interrupt.
When written to a logic 1, this bit enables the REI-P Interrupt.
When written to a logic 1, this bit enables the Payload Label Mismatch-Path (PLM-P)
Interrupt.
When written to a logic 1, this bit enables the STS Path Unequipped (Uneq-P)
Interrupt.
When written to a logic 1, this bit enables the Path Trace Interrupt.
to 0, reduced RDI functionality detection is performed.
Reserved, write to 0.
Mindspeed Technologies
Description
Description
™
ATM Physical Interface (PHY) Devices
28250-DSH-002-C
CX28250