cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 79

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

CX28250
ATM Physical Interface (PHY) Devices
2.6.5 Interrupts
28250-DSH-002-C
2.6.5.1 Interrupt
Routing
The CX28250’s interrupt indications can be classified as either single-event or
dual-event. A single-event interrupt is triggered by a status assertion. A
dual-event interrupt is triggered by either a status assertion or deassertion. Both
types of interrupts are further described in the following examples.
data bus, an interrupt is generated on ParErrInt, bit 7 in the TXCELLINT register
(0x40). This bit is cleared when read.
corresponding RXCELLINT register (0x41) is set to 1. This bit is cleared when
the register is read. Once cell delineation is recovered, bit 7 is set to 1 again,
generating another interrupt.
disable or mask interrupts as required.
The CX28250 uses two levels of interrupt indications. The first level consists of
section, line, path, APS, receive, and transmit interrupt indications. The second
level summarizes first-level interrupts and indicates one-second interrupts.
PTHINT, APSINT, TXCELLINT, and RXCELLINT. Each interrupt bit in these
registers can be disabled in the corresponding ENSEC, ENLIN, ENPTH, ENAPS,
ENCELLT, or ENCELLR registers, respectively. The result is then ORed into the
appropriate bit in the SUMINT register.
SUMINT register. It also includes the OneSecInt indications. Each interrupt bit in
these registers can be disabled in the corresponding ENSUMINT register. The
result is ORed to the MInt* pin. The MInt* pin can be enabled or disabled by
setting the EnIntPin (bit 6) in the GEN register (0x00).
Single-event interrupt: When a parity error occurs on the UTOPIA transmit
Dual-event interrupt: When LOCD occurs, LOCDInt, bit 7 of the
All interrupt bits have a corresponding enable bit. This allows software to
The first level interrupt indications are located in registers SECINT, LININT,
The second level consists of summary interrupt indications, located in the
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2.0 Functional Description
2.6 Microprocessor Interface
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