cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 141

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

CX28250
ATM Physical Interface (PHY) Devices
0x2D—RXIDL2 (Receive Idle Cell Header Control Register 2)
The RXIDL2 register contains the second byte of the Receive Idle Cell Header. It defines ATM idle cells for the
cell receiver. Idle cells are counted and discarded from the received stream if DelIdle, bit 6 in the CVAL register
(0x08), is set to 1. This header consists of 32 bits divided among four registers.
0x2E—RXIDL3 (Receive Idle Cell Header Control Register 3)
The RXIDL3 register contains the third byte of the Receive Idle Cell Header. It defines ATM idle cells for the
cell receiver. Idle cells are counted and discarded from the received stream if DelIdle, bit 6 in the CVAL register
(0x08), is set to 1. This header consists of 32 bits divided among four registers.
28250-DSH-002-C
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RxIdl3[7]
RxIdl3[6]
RxIdl3[5]
RxIdl3[4]
RxIdl3[3]
RxIdl3[2]
RxIdl3[1]
RxIdl3[0]
RxIdl2[7]
RxIdl2[6]
RxIdl2[5]
RxIdl2[4]
RxIdl2[3]
RxIdl2[2]
RxIdl2[1]
RxIdl2[0]
Name
Name
Mindspeed Technologies
These bits hold the Receive Idle cell header for Octet 3 of the incoming cell.
These bits hold the Receive Idle cell header for Octet 2 of the incoming cell.
Description
Description
™
4.0 Registers
4.1 Registers
4-43