cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 154

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

4.0 Registers
4.1 Registers
0x1C—TXHDR1 (Transmit Cell Header Control Register 1)
The TXHDR1 register contains the first byte of the Transmit Cell Header. This header consists of 32 bits
divided among four registers. Cell generation is described in detail in
0x1D—TXHDR2 (Transmit Cell Header Control Register 2)
The TXHDR2 register contains the second byte of the Transmit Cell Header. This header consists of 32 bits
divided among four registers. Cell generation is described in detail in
4-56
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TxHdr1[7]
TxHdr1[6]
TxHdr1[5]
TxHdr1[4]
TxHdr1[3]
TxHdr1[2]
TxHdr1[1]
TxHdr1[0]
TxHdr2[7]
TxHdr2[6]
TxHdr2[5]
TxHdr2[4]
TxHdr2[3]
TxHdr2[2]
TxHdr2[1]
TxHdr2[0]
Name
Name
These bits hold the Transmit Header values for Octet 1 of the outgoing cell. Insertion of
the bits is controlled by register 0x04 (CGEN).
These bits hold the Transmit Header values for Octet 2 of the outgoing cell. Insertion of
the bits is controlled by the CGEN register (0x04).
Mindspeed Technologies
GFC bits. (Bit 7 is the GFC MSB.)
VPI bits. (Bit 3 is the GFC MSB.)
VPI bits. (Bit 4 is the VPI LSB.)
VCI bits. (BIT 3 is the VCI MSB.)
Description
Description
Section
Section
™
ATM Physical Interface (PHY) Devices
2.4.
2.4.
28250-DSH-002-C
CX28250