cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 32

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

1.0 Product Description
1.4 CX28250 Pinout and Pin Descriptions
Table 1-1. CX28250 Pin Definitions (10 of 12)
1-16
URxData[0]
URxData[1]
URxData[2]
URxData[3]
URxData[4]
RxData[5]
URxData[6]
URxData[7]
URxData[8]
URxData[9]
URxData[10]
URxData[11]
URxData[12]
URxData[13]
URxData[14]
URxData[15]
URxPrty
URxSOC
UBusWidth
Pin Label
UTOPIA Receive Data
Bus
UTOPIA Receive
Parity
UTOPIA Receive Start
of Cell
UTOPIA Bus Width
Signal Name
Mindspeed Technologies
D11
H12
No.
B12
A12
B11
A11
B10
A10
B14
B9
A9
C9
D9
B8
C8
A7
B7
A6
C6
Type
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
The data bus is driven from the ATM layer to the PHY
layer. URxData[15] is the MSB of the high octet and
URxData[7] is the MSB of the lower octet. To support
multiple PHY configurations, URxData can be placed
in a high-impedance state which is enabled only when
URxEnb* is asserted.
The data bus parity is odd parity for URxData[7:0],
driven by the PHY layer. In 16-bit mode, this is the
odd parity bit over URxData[15:0]. To support
multiple PHY configurations, URxPrty can be placed
in a high-impedance state which is enabled only in
cycles following those with URxEnb* asserted.
The Start of Cell signal is active high. It is asserted by
the PHY layer when RxData contains the first valid
byte of the cell. In support of multiple PHY
configurations, when URxEnb* is asserted, the
URxData and URxSOC PHY layer outputs change to a
high-impedance state. URxData and URxSOC must be
enabled only in cycles following those with URxEnb*
asserted.
This pin selects the default value for the UTOPIA bus
width. The state of this pin will be latched into bit 3 of
the UTOP1 register on power-up or reset.
UTOPIA. It has an internal pull-down resistor. Note
that this pin is a “no connect” on the CX28250-23.
Tie it low for 16 bit UTOPIA; tie high for 8 bit
™
ATM Physical Interface (PHY) Devices
(1)
Description
28250-DSH-002-C
CX28250
(1)