cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 138

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

4.0 Registers
4.1 Registers
0x19—RXG1 (Receive G1 Overhead Status Register)
The RXG1 register is used to provide path status information to the originating terminal.
0x24—RXHDR1 (Receive Cell Header Control Register 1)
The RXHDR1 register contains the first byte of the Receive Cell Header. The header values direct ATM cells to
the UTOPIA port. If an incoming ATM cell header matches the value in the header register, the cell is directed
to the UTOPIA port. Receive Header Mask registers further qualify ATM cell reception. This header consists of
32 bits divided among four registers.
4-40
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
x
x
x
0
0
0
0
0
0
0
0
RxHdr1[7]
RxHdr1[6]
RxHdr1[5]
RxHdr1[4]
RxHdr1[3]
RxHdr1[2]
RxHdr1[1]
RxHdr1[0]
RxRDI[5]
RxRDI[6]
RxRDI[7]
Name
Name
—
—
—
—
—
Reserved, set to 0.
Reserved, set to 0.
Reserved, set to 0.
Reserved, set to 0.
Received value of bit 5 of the G1 octet.
Received value of bit 6 of the G1 octet.
Received value of bit 7 of the G1 octet.
Reserved, set to 0.
These bits hold the Receive Header values for Octet 1 of the incoming cell.
Mindspeed Technologies
Description
Description
™
ATM Physical Interface (PHY) Devices
28250-DSH-002-C
CX28250