cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 33

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

CX28250
ATM Physical Interface (PHY) Devices
Table 1-1. CX28250 Pin Definitions (11 of 12)
28250-DSH-002-C
UtopMode
URxClAv
PWR
Analog PWR
Pin Label
UTOPIA Mode
UTOPIA Receive Cell
Available
3.3 V Digital Supply
Voltage
3.3 V Analog Supply
Voltage
Signal Name
Mindspeed Technologies
N14
D10
D13
No.
C12
C10
K11
M5
M7
M9
C7
D1
D3
D8
N9
J2
J3
L5
Type
TTL
TTL
—
—
I/O
—
—
O
I
This pin selects the default value for the UTOPIA
mode. The state of this pin will be latched into bit 5 of
the UTOP1 register on power-up or reset.
level 2. It has an internal pull-up resistor. Note that
this pin is a “no connect” on the CX28250-23.
This signal indicates FIFO empty or Cell Buffer
Available. For octet-level flow control, this signal is
active low from the PHY layer to the ATM layer. It is
asserted to indicate that in the current cycle there is
no valid data for delivery to the ATM layer.
environment, URxClAv is an active high signal with
high impedance potential going from the multi-PHY
layer to the ATM layer. A polled multi-PHY device
drives this signal only during each cycle following
one with its address on the URxAddr lines. The polled
multi-PHY device asserts URxClAv high to indicate it
has a complete cell available for transfer to the ATM
layer, otherwise it deasserts the signal.
Digital power supply pins.
Analog power pins. See
Tie it low for UTOPIA level 1; tie it high for UTOPIA
For cell-level flow control in an multi-PHY
™
1.4 CX28250 Pinout and Pin Descriptions
Description
Section
1.0 Product Description
3.2.1.
(1)
1-17