cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 31

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

CX28250
ATM Physical Interface (PHY) Devices
Table 1-1. CX28250 Pin Definitions (9 of 12)
28250-DSH-002-C
UTxSOC
UTxClAv
URxClk
URxEnb*
URxAddr[0]
URxAddr[1]
URxAddr[2]
URxAddr[3]
URxAddr[4]
Pin Label
UTOPIA Transmit
Start of Cell
UTOPIA Transmit Cell
Available
UTOPIA Receive
Clock
UTOPIA Receive
Enable
UTOPIA Receive
Address
Signal Name
Mindspeed Technologies
No.
E13
E12
C14
C13
D6
A5
C5
B5
D5
Type
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
I/O
O
I
I
I
I
I
I
I
I
The Start of Cell signal is active high. It is asserted by
the ATM layer during cycles when UTxData contains
the first valid byte of the cell.
This signal indicates FIFO full or Cell Buffer Available.
For octet-level flow control, this signal is active low
from the PHY layer to the ATM layer. It is asserted to
indicate that a maximum of four more transmit data
writes will be accepted.
environment, UTxClAv is an active high signal with
high impedance potential going from the multi-PHY
layer to the ATM layer. A polled multi-PHY device
drives this signal only during each cycle following
one with its address on the UTxAddr lines. The polled
multi-PHY device asserts UTxClAv high to indicate it
can accept the transfer of a complete cell, otherwise it
deasserts the signal.
The data transfer/interface byte clock is provided by
the ATM layer to the PHY layer for synchronizing
transfers on URxData.
The enable receive data signal is active low. It is
asserted by the ATM layer to indicate that URxData
and URxSOC will be sampled at the end of the next
cycle. In support of multiple PHY configurations,
when URxEnb* is asserted, the URxData and
URxSOC PHY layer outputs change to a
high-impedance state. URxData and URxSOC must be
enabled only in cycles following those with URxEnb*
asserted.
This is the address of the PHY device being selected.
It is driven from the ATM to the multi-PHY layer to
poll and select the appropriate multi-PHY device.
URxAddr [4] is the MSB. Each multi-PHY device must
maintain its address. Address 31 indicates a null PHY
port.
For cell-level flow control in an multi-PHY
™
1.4 CX28250 Pinout and Pin Descriptions
Description
(1)
1.0 Product Description
1-15