cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 50

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

2.0 Functional Description
2.3 SONET/SDH Framer and Overhead Processor
Table 2-4. LStatOut Configuration
2-14
NOTE(S):
(1)
(2)
0
1
x
x
x
x
Any combination of the four Data Link control bits is allowed and overrides the StatPinMode bit for StatOut[7:2]. StatOut pins not being used
for the Data Link operate as determined by StatPinMode.
StatOut[1] and StatOut[0] are only controlled by StatPinMode and are unaffected by the Data Link control bits.
0
0
x
x
1
x
2.3.2.4 D1-D3
2.3.2.3 B1
0
0
x
x
x
1
0
0
1
x
x
x
The Section Bit Interleaved Parity (BIP)-8 byte, B1, is allocated for section layer
error monitoring. This byte contains a BIP-8 code using even parity. The code is
calculated using all the bits of the previous STS-3c/STM-1 frame after
scrambling. Each piece of section terminating equipment calculates the B1 byte
of the current STS-3c/STM-1 frame and compares it with the B1 byte received
from the next STS-3c/STM-1 frame. If the B1 bytes match, there is no error. If the
B1 bytes do not match, the alarm indicator is set. The B1 bytes of the rest of the
STS-3c/STM-1 frame are not defined. As many as 64 kb errors per second can be
detected. These section level bit errors are gathered in a 16-bit counter (registers
B1CNTL [0x54] and B1CNTH [0x55]). The counter is latched so that it can
continue to count while the latch is being read. This prevents the loss of any error
counts.
The CX28250 provides access to two data link channels, D1—D3 and D4—D12,
via the StatOut pins and the TxDL pin. Independent control is provided for
receiving and/or transmitting data over each channel, as outlined in
0
0
1
x
x
x
OutStat[7] OutStat[6] OutStat[5] OutStat[4] OutStat[3] OutStat[2] OutStat[1] OutStat[0]
Rx Clock
Rx Clock
Output
Output
Note 1
Note 1
Mindspeed Technologies
LOS
Rx Data
Rx Data
Output
Output
Note 1
Note 1
OOF
Indicator
Indicator
Channel
Channel
Note 1
Note 1
LOP
Rx
Rx
Tx Clock
Tx Clock
Note 1
Note 1
Output
Output
AIS-L
™
ATM Physical Interface (PHY) Devices
Tx Channel
Tx Channel
Indicator
Indicator
Note 1
Note 1
RDI-L
Tx Cell
Tx Cell
Note 1
Note 1
AIS-P
Sync
Sync
28250-DSH-002-C
Note 2
Note 2
Note 2
Note 2
RDI-P
Table
CX28250
2-4.
Note 2
Note 2
Note 2
Note 2
LOCD