cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 76

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

2.0 Functional Description
2.6 Microprocessor Interface
2.6.1 Microprocessor Clock
2-40
2.6 Microprocessor Interface
The microprocessor interface transfers control and status information in 8-bit data
transfers between the external microprocessor and CX28250 by means of write
and/or read access to internal registers. This interface allows the microprocessor
to configure the CX28250 by writing various control registers. These control
registers can also be read for configuration confirmation. This interface also
provides the ability to read the device’s current condition via its status registers
and counters. Summary status is available for rapid interrupt identification.
asynchronous, SRAM-like interface and a synchronous interface. The
MSyncMode pin determines which mode is active.
as follows: MAcsSel, MCs*, MRd*, MWr*, MInt*, MRdy, MAddr, MData. In
this mode, the MRd* and MWr* strobes direct the data transfers. The
asynchronous interface has two secondary operating modes: a high-performance
access mode and a low-power access mode. The MAcsSel pin determines which
access mode is active. These modes allow for trade-offs between speed and power
required for various applications.
as follows: MClk, MCs*, MW/R*, MAs*, MInt*, MAddr, MData. In this mode,
the timing of these signals is synchronized to MClk, which is intended to be
directly driven by the external microprocessor. The synchronous interface is
compatible with the Bt8230 and Bt8233 SAR devices, providing no-wait-state
operation.
Two pins determine the behavior of the micro interface clock circuits: MClk (pin
L3) and MsyncMode (pin M1).
access or low power access. In either case, the microprocessor clock is internally
derived from the LPLLClk input. When tied high, for high speed access, the
internal clock samples the microprocessor inputs at an 80 ns rate. When tied low,
for low power, the internal clock samples the inputs at 130 ns.
The microprocessor interface has two primary modes of operation: an
For the asynchronous interface, the microprocessor interface pins are defined
For the synchronous interface, the microprocessor interface pins are defined
• MClk-MAcsSel: This is a dual mode pin. If the device is configured for
• MSyncMode selects either the synchronous mode or the asynchronous
When using the asynchronous mode, this pin selects either the high speed
synchronous operation this is the clock input for the microprocessor
interface. See the timing diagrams in
mode. When tied high the async mode is selected; this is used mainly for
Mindspeed SARs. When tied low, it configures the device for the async
mode as used by most general purpose processors.
Mindspeed Technologies
™
ATM Physical Interface (PHY) Devices
Chapter
5.0.
28250-DSH-002-C
CX28250