cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 117

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

CX28250
ATM Physical Interface (PHY) Devices
0x01—CLKREC (Clock Recovery Control Register)
The CLKREC register controls the clock recovery and loopback testing capabilities of the device. See
Table 4-10
Table 4-10. CLKREC Valid Configurations
28250-DSH-002-C
ExtClkRec
Bit
7
6
5
4
3
2
1
0
0
0
1
0
X
X
1
X
Default
for a list of the valid configuration for the CLKREC register.
0
0
0
0
0
0
0
0
TxClkSel(1)
0
0
X
0
X
X
X
1
TxClkSel(1)
TxClkSel(0)
ExtClkRec
LinLoop1
LinLoop2
InvRxClk
InvTxClk
SrcLoop
Name
NOTE:
TxClkSel(0)
X
X
X
X
0
1
0
1
Only one loopback may be selected at a time.
When written to a logic 1, this bit inverts the Transmit Clock output on LTxClk0+/-.
This bit selects the type of Receive Clock sampling when using external clock recovery
(Bit 5 is written to 1). When written to 1, the receive clock samples data on the falling
edge. When written to 0, the receive clock samples data on the rising edge. When Bit 5
is written to 0, the setting of this bit has no effect.
When written to a logic 1, this bit enables External Clock Recovery. When enabled, the
internal clock recovery circuit is bypassed. When written to 0, internal clock recovery
is used.
These bits in combination provide the Transmit Clock Select as follows:
When written to a logic 1, this bit invokes a source loopback. The receiver clock and
data inputs are connected to the transmitter clock and data inputs. See
more information. When source loopback is enabled, bit 5 of this register must be set
to 0.
When written to a logic 1, this bit enables Line Loopback 1. When enabled, the
received line clock and data inputs are connected to line transmitter outputs. See
Section 2.7
When written to a logic 1, this bit enables Line Loopback 2. When enabled, the
received UTOPIA clock and data outputs are connected to UTOPIA transmitter inputs.
The UTOPIA bus is placed in a high-impedance state. See
information.
Mindspeed Technologies
00—TX clock synthesized from external 19.44 MHz input on PLLClk
01—TX clock synthesized from recovered receive clock (loop timing)
10—TX clock from external 155.52 MHz input on TxClkI+/-
11—Reserved; do not use
SrcLoop
X
0
0
0
1
0
0
1
for more information.
LinLoop 1
0
0
0
0
1
0
0
X
Description
LinLoop 2
™
X
0
0
0
0
0
1
0
Normal operation 19.44 MHz
Transmit Clock (default)
Normal operation Loop timed
External clock recovery mode
Source Loopback
Line Loopback 1. See
Section
Line Loopback 2. See
Section
ILLEGAL—do not use
ILLEGAL—do not use
Section 2.7
2.7.
2.7.
Description
for more
Section 2.7
4.0 Registers
4.1 Registers
4-19
for