cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 156

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

4.0 Registers
4.1 Registers
0x20—TXIDL1 (Transmit Idle Cell Header Control Register 1)
The TXIDL1 register contains the first byte of the Transmit Idle Cell Header. It contains the header value that is
inserted in idle cells transmitted from the device. This header consists of 32 bits divided among four registers.
Cell generation is described in detail in
0x21—TXIDL2 (Transmit Idle Cell Header Control Register 2)
The TXIDL2 register contains the second byte of the Transmit Idle Cell Header. It contains the header value that
is inserted in idle cells transmitted from the device. This header consists of 32 bits divided among four registers.
Cell generation is described in detail in
4-58
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TxIdl2[7]
TxIdl2[6]
TxIdl2[5]
TxIdl2[4]
TxIdl2[3]
TxIdl2[2]
TxIdl2[1]
TxIdl2[0]
TxIdl1[7]
TxIdl1[6]
TxIdl1[5]
TxIdl1[4]
TxIdl1[3]
TxIdl1[2]
TxIdl1[1]
TxIdl1[0]
Name
Name
These bits hold the Transmit Idle Cell Header values for Octet 2 of the outgoing cell.
These bits hold the Transmit Idle Cell Header values for Octet 1 of the outgoing cell.
Mindspeed Technologies
Section
Section
VPI bits. (Bit 4 is the VPI LSB.)
VCI bits. ((Bit 3 is the VCI MSB.)
GFC bits. (Bit 7 is the GFC MSB.)
VPI bits. (Bit 3 is the VPI MSB.)
2.4.
2.4.
Description
Description
™
ATM Physical Interface (PHY) Devices
28250-DSH-002-C
CX28250