cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 161

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

CX28250
ATM Physical Interface (PHY) Devices
0x12—TXS1 (Transmit S1 Overhead Control Register)
The TXS1 register controls the S1 byte in the transport overhead. This byte is allocated for transporting
synchronization status messages and is defined only for the first STS-1 of the STS-3c signal. These messages
provide an indication of the quality level of the synchronization source of the SONET signal.
0x0C—TXSEC (Transmit Section Overhead Control Register)
The TXSEC register controls transmission of various octets in the Section Overhead of the SONET frame.
28250-DSH-002-C
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TxFrmPulOut
TxFrmPulPol
EnTxSecDL
DisTxScr
InsAllZer
DisA1A2
EnSecTr
TxS1[1]
TxS1[2]
TxS1[3]
TxS1[4]
TxS1[5]
TxS1[6]
TxS1[7]
TxS1[8]
Name
Name
DisB1
When written to a logic 1, this bit disables the Transmit Frame Scrambler. When
written to 0, scrambling is enabled.
When written to a logic 1, this bit enables the Transmit D1/D2/D3 bytes of the Data
Link. When written to 0, these bytes are forced to all 00.
When written to a logic 1, this bit enables the Section Trace Message (J0). When
written to 0, the J0 byte contains 01. The Z0/Z0 bytes contain 02/03 regardless of the
Bit 5 setting.
When this bit is written to a logic 1, the A1/A2 Overhead bytes are forced to 00, When
written to 0, the A1/A2 Overhead bytes contain their default values (F6/28).
When written to a logic 1, this bit disables the BIP calculation for the Section
Overhead. When disabled, the B1 byte is set to 00. When written to 0, the BIP
calculation is enabled, and the result is placed in the B1 byte.
When written to a logic 1, this bit inserts 0s after the Transmit Frame Scrambler
output. When written to 0, cell/overhead data is transmitted.
This bit selects the type of output sent to the TxFrameRef pin. When written to a logic
1, the transmit octet clock (19.44 MHz) is present. When written to a logic 0, a
Transmit Frame Pulse (8 kHz) is present.
This bit selects the polarity of the TxFrameRef pin. When written to a logic 1, the frame
pulse output is an active high. When written to 0, the frame pulse output is an active
low.
Transmit value for S1 Overhead Octet—bit 1 (MSB)
Transmit value for S1 Overhead Octet—bit 2
Transmit value for S1 Overhead Octet—bit 3
Transmit value for S1 Overhead Octet—bit 4
Transmit value for S1 Overhead Octet—bit 5
Transmit value for S1 Overhead Octet—bit 6
Transmit value for S1 Overhead Octet—bit 7
Transmit value for S1 Overhead Octet—bit 8 (LSB)
Mindspeed Technologies
Description
Description
™
4.0 Registers
4.1 Registers
4-63