cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 123

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

CX28250
ATM Physical Interface (PHY) Devices
0x34—ENSUMINT (Summary Interrupt Mask Control Register)
The ENSUMINT register determines which of the interrupts listed in register 0x3C (SUMINT) are observed on
the MInt*.
0x06—ERRINS (Error Insertion Control Register)
The ERRINS register controls error insertion into various octets for diagnostic purposes. These bits are cleared
automatically by internal circuitry after the indicated error insertion has taken place. Clearing takes precedence
over a simultaneous write operation to this register.
28250-DSH-002-C
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
EnOneSecInt
EnOnesDet
EnRxCellInt
InsHECErr
EnTxCellInt
InsB2Err1
InsB2Err2
InsB2Err3
InsB1Err
InsB3Err
EnAPSInt
InsFrErr
EnSecInt
EnPthInt
EnLinInt
Name
Name
—
When written to a logic 1, this bit inverts the A1 bytes for one transmit frame. When
written to 0, the A1 bytes are not inverted.
This bit XORs the B1 BIP calculation with the ERRPAT register (0x07) value and inserts
the new value into the transmitted B1 byte for one transmit frame only.
This bit XORs the B2-1 BIP calculation with the ERRPAT register (0x07) value and
inserts the new value into the transmitted B2-1 byte for one transmit frame only.
This bit XORs the B2-2 BIP calculation with the ERRPAT register (0x07) value and
inserts the new value into the transmitted B2-2 byte for one transmit frame only.
This bit XORs the B2-3 BIP calculation with the ERRPAT register (0x07) value and
inserts the new value into the transmitted B2-3 byte for one transmit frame only.
This bit XORs the B3 BIP calculation with the ERRPAT register (0x07) value and inserts
the new value into the transmitted B3 byte for one transmit frame only.
This bit XORs the HEC byte with the ERRPAT register (0x07) value and inserts the new
value into the transmitted HEC byte for one transmit cell only.
When written to a logic 1, this bit allows the CX28250 to detect an “all one” pattern on
the receive interface and declare LOS.
When written to a logic 1, this bit enables the SONET Section Overhead interrupt. It is
a global disable for the SONET Section interrupt sources.
When written to a logic 1, this bit enables the SONET Line Overhead interrupt. It is a
global disable for the SONET Line interrupt sources.
When written to a logic 1, this bit enables the SONET Path Overhead interrupt. It is a
global disable for the SONET Path interrupt sources.
When written to a logic 1, this bit enables the One Second Interrupt generated by the
OneSecIn pin to appear on the MInt* output pin.
Reserved, set to 0.
When written to a logic 1, this bit enables the APS interrupt. It is a global disable for
the APS interrupt sources.
When written to a logic 1, this bit enables the Receive Cell Interrupt. It is a global
disable for the RxCellInt interrupt sources.
When written to a logic 1, this bit enables the Transmit Cell Interrupt. It is a global
disable for the TxCellInt interrupt sources.
Mindspeed Technologies
Description
Description
™
4.0 Registers
4.1 Registers
4-25