cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 127

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

CX28250
ATM Physical Interface (PHY) Devices
0x32—IDLMSK3 (Receive Idle Cell Mask Control Register 3)
The IDLMSK3 register contains the third byte of the Receive Idle Cell Mask. It modifies the ATM cell screen in
the Receive Cell Header register. Setting a bit in the Mask register causes the corresponding bit in the received
ATM cell header to be disregarded for screening. For example, setting RXMSK1, bit 0 to 1, causes ATM cells to
be accepted with either 1 or 0 in the octet 1, bit 0 position. Combinations of Receive Header Mask bits can
select groups of ATM VPI/VCIs for reception. This mask consists of 32 bits divided among four registers.
0x33—IDLMSK4 (Receive Idle Cell Mask Control Register 4)
The IDLMSK4 register contains the fourth byte of the Receive Idle Cell Mask. It modifies the ATM cell screen
in the Receive Cell Header register. Setting a bit in the Mask register causes the corresponding bit in the
received ATM cell header to be disregarded for screening. For example, setting RXMSK1, bit 0 to 1, causes
ATM cells to be accepted with either 1 or 0 in the octet 1, bit 0 position. Combinations of Receive Header Mask
bits can select groups of ATM VPI/VCIs for reception. This mask consists of 32 bits divided among four
registers.
28250-DSH-002-C
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IdlMsk4[7]
IdlMsk4[6]
IdlMsk4[5]
IdlMsk4[4]
IdlMsk4[3]
IdlMsk4[2]
IdlMsk4[1]
IdlMsk4[0]
IdlMsk3[7]
IdlMsk3[6]
IdlMsk3[5]
IdlMsk3[4]
IdlMsk3[3]
IdlMsk3[2]
IdlMsk3[1]
IdlMsk3[0]
Name
Name
Mindspeed Technologies
These bits hold the Receive Idle cell header mask for Octet 4 of the incoming cell.
These bits hold the Receive Idle cell header mask for Octet 3 of the incoming cell.
Description
™
Description
4.0 Registers
4.1 Registers
4-29