cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 164

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

4.0 Registers
4.1 Registers
0x4E—UNCCNT (Uncorrected HEC Error Counter)
The UNCCNT counter tracks the number of uncorrected HEC errors.
0x0A—UTOP1 (UTOPIA Control Register 1)
The UTOP1 register controls the mode of operation for the UTOPIA interface.
4-66
NOTE(S):
(1)
Bit
Bit
Pins UtopMode and BusWidth can override the defaults. Refer to
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
1
0
x
x
x
x
x
x
x
x
0
0
1
0
0
0
(1)
(1)
UncCnt[7]
UncCnt[6]
UncCnt[5]
UncCnt[4]
UncCnt[3]
UncCnt[2]
UncCnt[1]
UncCnt[0]
Name
Handshake
UtopMode
BusWidth
Odd/Even
RxReset
TxFill[1]
TxFill[0]
TxReset
Name
Uncorrected HEC Error counter bit 7 (MSB).
Uncorrected HEC Error counter bit 6.
Uncorrected HEC Error counter bit 5.
Uncorrected HEC Error counter bit 4.
Uncorrected HEC Error counter bit 3.
Uncorrected HEC Error counter bit 2.
Uncorrected HEC Error counter bit 1.
Uncorrected HEC Error counter bit 0 (LSB).
Mindspeed Technologies
When written to a logic 1, this bit resets the transmit FIFO pointers. This reset
must be used as a test function since it can create short cells.
When written to a logic 1, this bit resets the receive FIFO pointers. This reset
must be used as a test function since it can create short cells.
When written to a logic 1, this bit enables UTOPIA Level 2 Mode. When written
to a logic 0, UTOPIA Level 1 operation is enabled.
When written to a logic 1, this bit enables cell handshaking. When written to a
logic 0, octet handshaking is enabled.
When written to a logic 1, this bit enables the 8-bit bus. When written to a logic
0, the 16-bit bus is enabled.
This bit determines Odd/Even Parity. When written to a logic 1, even parity is
generated and checked. When written to a logic 0, odd parity is generated and
checked.
These bits set the Transmit FIFO Fill Level threshold for UTxClAv pin.
00—The TxClAv line will be asserted if the UTOPIA FIFO can accept at least 1
more complete cell.
01—The TxClAv line will be asserted only if the UTOPIA FIFO has room for least
2 more cells.
10—The TxClAv line will be asserted only if the UTOPIA FIFO has room for at
least 3 more cells.
11—The TxClAv line will be asserted only if the UTOPIA FIFO can accept at least
3 more cells.
Table 1-1
for a description of these pins.
Description
™
Description
ATM Physical Interface (PHY) Devices
28250-DSH-002-C
CX28250