cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 157

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

CX28250
ATM Physical Interface (PHY) Devices
0x22—TXIDL3 (Transmit Idle Cell Header Control Register 3)
The TXIDL3 register contains the third byte of the Transmit Idle Cell Header. It contains the header value that is
inserted in idle cells transmitted from the device. This header consists of 32 bits divided among four registers.
Cell generation is described in detail in
0x23—TXIDL4 (Transmit Idle Cell Header Control Register 4)
The TXIDL4 register contains the fourth byte of the Transmit Idle Cell Header. It contains the header value that
is inserted in idle cells transmitted from the device. This header consists of 32 bits divided among four registers.
Cell generation is described in detail in
28250-DSH-002-C
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
TxIdl4[7]
TxIdl4[6]
TxIdl4[5]
TxIdl4[4]
TxIdl4[3]
TxIdl4[2]
TxIdl4[1]
TxIdl4[0]
TxIdl3[7]
TxIdl3[6]
TxIdl3[5]
TxIdl3[4]
TxIdl3[3]
TxIdl3[2]
TxIdl3[1]
TxIdl3[0]
Name
Name
These bits hold the Transmit Idle Cell Header values for Octet 3 of the outgoing cell.
These bits hold the Transmit Idle Cell Header values for Octet 4 of the outgoing cell.
Cell Loss Priority bit
Mindspeed Technologies
Section
Section
VCI bits
VCI bits. (Bit 4 is the VCI LSB.)
Payload-type bits
2.4.
2.4.
Description
Description
™
4.0 Registers
4.1 Registers
4-59