cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 111
cx28250
Manufacturer Part Number
cx28250
Description
Cx28250 Atm Physical Interface Phy Devices
Manufacturer
Mindspeed Technologies
Datasheet
1.CX28250.pdf
(213 pages)
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CX28250
ATM Physical Interface (PHY) Devices
0x09—APSTHRESH (APS Threshold Control Register)
The APSTHRESH register sets the threshold value for Signal Fail and Signal Degrade Alarm generation. Bits
7–4 are the signal fail threshold exponent (default = 10
(default = 10
0x55—B1CNTH (Section BIP Error Counter [High Byte])
The B1CNTH counter tracks the number of Section BIP errors.
28250-DSH-002-C
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
-6
0
0
1
1
0
1
1
0
x
x
x
x
x
x
x
x
).
SDThresh[3]
SDThresh[2]
SDThresh[1]
SDThresh[0]
SFThresh[3]
SFThresh[2]
SFThresh[1]
SFThresh[0]
B1Cnt[15]
B1Cnt[14]
B1Cnt[13]
B1Cnt[12]
B1Cnt[11]
B1Cnt[10]
B1Cnt[9]
B1Cnt[8]
Name
Name
Section BIP Error counter bit 15 (MSB).
Section BIP Error counter bit 14.
Section BIP Error counter bit 13.
Section BIP Error counter bit 12.
Section BIP Error counter bit 11.
Section BIP Error counter bit 10.
Section BIP Error counter bit 9.
Section BIP Error counter bit 8.
Threshold exponent value for setting signal fail status—Bit 3 (MSB)
Threshold exponent value for setting signal fail status—Bit 2
Threshold exponent value for setting signal fail status—Bit 1
Threshold exponent value for setting signal fail status—Bit 0 (LSB)
Threshold exponent value for setting signal degrade status—Bit 3 (MSB)
Threshold exponent value for setting signal degrade status—Bit 2
Threshold exponent value for setting signal degrade status—Bit 1
Threshold exponent value for setting signal degrade status—Bit 0 (LSB)
Mindspeed Technologies
-3
) and bits 3–0 are the signal degrade threshold exponent
Description
Description
™
4.0 Registers
4.1 Registers
4-13
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