cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 25

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

CX28250
ATM Physical Interface (PHY) Devices
Table 1-1. CX28250 Pin Definitions (3 of 12)
28250-DSH-002-C
LPLLClk
MClk,
MAcsSel
MSyncMode
MCs*
Pin Label
Line Phase Loop
Lock Clock
Microprocessor
Clock, Access Time
Select
Microprocessor
Synchronous/Asynch
ronous Bus Mode
Select
Microprocessor Chip
Select
Signal Name
Mindspeed Technologies
No.
M1
P5
C1
L3
Type
TTL
TTL
TTL
TTL
I/O
I
I
I
I
19.44 Mhz reference clock input used by the CDR and
the transmit synthesizer PLLs.
the 155.52 Mhz clock from the line receive data. The
transmit synthesizer uses this clock to generate a
155.52 Mhz line transmit clock. This clock should
have an accuracy of ± 20 ppm.
When MSyncMode is set to a logic 1, the MClk pin is
a clock signal that samples the microprocessor
interface pins (MCs*, MW/R*, MAs*, MAddr[6:0],
MData[7:0]) on its rising edge. Additionally, the rising
edge of MClk may cause the microprocessor interface
output pins (MData[7:0], MInt*) to change states.
pin selects the asynchronous interface access time. A
logic 0 selects a power-saving access mode (130 ns)
while a logic 1 selects the high-performance access
mode (80 ns).
A logic 1 selects the synchronous bus mode
compatible with Mindspeed ATM SAR devices. In this
mode, the microprocessor pins are defined as
follows: MClk, MW/R*, MAs*, MCs*, MInt*, MAddr,
and MData. A logic 0 selects the asynchronous
SRAM-type bus mode. In this mode, the pins are
defined as follows: MAcsSel, MRd*, MWr*, MCs*,
MInt*, MAddr, and MData.
When MCs* is set to a logic 0, the device is enabled
for read and write accesses. When MCs* is set to a
logic 1, the device does not respond to input signal
transitions on MClk, MAcsSel; MW/R*, MRd*; or
MAs*, MWr*. Additionally, when MCs* is set to a
logic 1, the MData[7:0] pins are in a high-impedance
state but the Int* pin remains operational.
The CDR uses this clock as a reference to recover
When MSyncMode is set to a logic 0, the MAcsSel
™
1.4 CX28250 Pinout and Pin Descriptions
Description
1.0 Product Description
1-9