cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 139
cx28250
Manufacturer Part Number
cx28250
Description
Cx28250 Atm Physical Interface Phy Devices
Manufacturer
Mindspeed Technologies
Datasheet
1.CX28250.pdf
(213 pages)
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CX28250
ATM Physical Interface (PHY) Devices
0x25—RXHDR2 (Receive Cell Header Control Register 2)
The RXHDR2 register contains the second byte of the Receive Cell Header. The header values direct ATM cells
to the UTOPIA port. If an incoming ATM cell header matches the value in the header register, the cell is
directed to the UTOPIA port. Receive Header Mask registers further qualify ATM cell reception. This header
consists of 32 bits divided among four registers.
0x26—RXHDR3 (Receive Cell Header Control Register 3)
The RXHDR3 register contains the third byte of the Receive Cell Header. The header values direct ATM cells to
the UTOPIA port. If an incoming ATM cell header matches the value in the header register, the cell is directed
to the UTOPIA port. Receive Header Mask registers further qualify ATM cell reception. This header consists of
32 bits divided among four registers.
28250-DSH-002-C
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RxHdr2[7]
RxHdr2[6]
RxHdr2[5]
RxHdr2[4]
RxHdr2[3]
RxHdr2[2]
RxHdr2[1]
RxHdr2[0]
RxHdr3[7]
RxHdr3[6]
RxHdr3[5]
RxHdr3[4]
RxHdr3[3]
RxHdr3[2]
RxHdr3[1]
RxHdr3[0]
Name
Name
Mindspeed Technologies
These bits hold the Receive Header values for Octet 2 of the incoming cell.
These bits hold the Receive Header values for Octet 3 of the incoming cell.
Description
Description
™
4.0 Registers
4.1 Registers
4-41
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