cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 136

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cx28250

Manufacturer Part Number
cx28250
Description
Cx28250 Atm Physical Interface Phy Devices
Manufacturer
Mindspeed Technologies
Datasheet

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4.0 Registers
4.1 Registers
0x41—RXCELLINT (Receive Cell Interrupt Indication Status Register)
The RXCELLINT register indicates that a change of status has occurred within its affiliated status signals.
0x66—RXCNTH (Received Cell Counter [High Byte])
The RXCNTH counter tracks the number of received cells.
4-38
NOTE(S):
(1)
(2)
Bit
Bit
7
6
5
4
3
2
1
0
Dual event—Either a 0–> 1 or a 1 –> 0 transition on the corresponding status bit causes this interrupt to occur provided that
this interrupt has been enabled by the corresponding enable bit. Reading the interrupt register clears the interrupt.
Single event—A 0–> 1 transition on the corresponding status bit causes this interrupt to occur provided that this interrupt has
been enabled by the corresponding enable bit. Reading the interrupt register clears the interrupt.
7
6
5
4
3
2
1
0
Default
Default
0
x
x
x
x
x
x
x
0
0
0
0
0
x
x
x
NonZerGFCInt
NonMatchInt
HECCorrInt
CellRcvdInt
IdleRcvdInt
HECDetInt
LOCDInt
RxCnt[18]
RxCnt[17]
RxCnt[16]
Name
Name
(1)
(2)
(2)
(2)
(2)
(2)
(2)
When a logic 1 is read, this bit indicates that a Loss of Cell Delineation has occurred.
When a logic 1 is read, this bit indicates that a HEC Error has been detected.
Reserved, set to 0.
When a logic 1 is read, this bit indicates that a Cell Received Interrupt has occurred.
When a logic 1 is read, this bit indicates that an Idle Cell Received Interrupt has occurred.
When a logic 1 is read, this bit indicates that a Non-matching Cell Received Interrupt has
occurred.
When a logic 1 is read, this bit indicates that a Non-zero GFC Received Interrupt has
occurred.
When a logic 1 is read, this bit indicates that a HEC Error has been corrected.
Reserved, set to 0.
Reserved, set to 0.
Reserved, set to 0.
Reserved, set to 0.
Reserved, set to 0.
Received cell counter bit 18 (MSB).
Received cell counter bit 17.
Received cell counter bit 16.
Mindspeed Technologies
Description
Description
ATM Physical Interface (PHY) Devices
28250-DSH-002-C
CX28250

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