cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 30

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

1.0 Product Description
1.4 CX28250 Pinout and Pin Descriptions
Table 1-1. CX28250 Pin Definitions (8 of 12)
1-14
UTxClk
UTxEnb*
UTxAddr[0]
UTxAddr[1]
UTxAddr[2]
UTxAddr[3]
UTxAddr[4]
UTxData[0]
UTxData[1]
UTxData[2]
UTxData[3]
UTxData[4]
UTxData[5]
UTxData[6]
UTxData[7]
UTxData[8]
UTxData[9]
UTxData[10]
UTxData[11]
UTxData[12]
UTxData[13]
UTxData[14]
UTxData[15]
UTxPrty
Pin Label
UTOPIA Transmit
Clock
UTOPIA Transmit
Enable
LSB
UTOPIA Transmit
Address
MSB
UTOPIA Transmit
Data
UTOPIA Transmit
Parity Input
Signal Name
Mindspeed Technologies
M12
M14
D14
N12
N13
H13
H14
H11
G12
G14
G13
No.
E11
P12
P13
L13
L14
K13
K14
E14
J14
J12
J11
F14
F13
Type
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
The data transfer/interface byte clock is provided by
the ATM layer to the PHY layer for synchronizing
transfers on UTxData.
The enable data transfers signal is active low. It is
asserted by the ATM layer during cycles when
UTxData contains valid cell data.
These pins are the address of the PHY device being
selected. The address is driven from the ATM to the
multi-PHY layer to poll and select the appropriate
multi-PHY device. Each multi-PHY device must
maintain its address. Address 31 indicates a null PHY
port.
The data bus is driven from the ATM layer to the PHY.
UTxData[15] is the MSB of the high octet and
UTxData[7] is the MSB of the lower octet.
The Transmit Data bus checks for odd parity over
UTxData [7:0] coming from the ATM layer. In 16-bit
mode, it checks for odd parity over UTxData[15:0].
™
ATM Physical Interface (PHY) Devices
Description
28250-DSH-002-C
CX28250