cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 119

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

CX28250
ATM Physical Interface (PHY) Devices
0x3A—ENAPS (APS Interrupt Mask Control Register)
The ENAPS register controls which of the interrupts listed in the APSInt register (0x42) appear on the MInt*
pin, provided that EnAPSInt (bit 2) in the ENSUMINT register (0x34) is enabled, and EnIntPin (bit 6) in the
GEN register (0x00) is enabled.
0x39—ENCELLR (Receive Cell Interrupt Mask Control Register)
The ENCELLR register controls which of the interrupts listed in the RxCellInt register (0x41) appear on the
MInt* pin, provided that EnRxCellInt (bit 1) in the ENSUMINT register (0x34) is enabled, and EnIntPin (bit 6)
in the GEN register (0x00) is enabled.
28250-DSH-002-C
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
1
0
0
1
1
1
1
1
0
1
1
1
1
EnSigDegrade
EnB3Degrade
EnNonZerGFC
EnNonMatch
EnHECCorr
EnCellRcvd
EnIdleRcvd
EnHECDet
EnSigFail
EnB3Fail
EnPSBF
EnLOCD
Name
Name
—
—
—
—
Reserved, set to 0.
Reserved, set to 0.
Reserved, set to 0.
When written to a logic 1, this bit enables the Protection Switch Byte Failure (PSBF)
Interrupt.
When written to a logic 1, this bit enables the B3 Failure Interrupt.
When written to a logic 1, this bit enables the B3 Degrade Interrupt.
When written to a logic 1, this bit enables the Signal Failure (SF) Interrupt.
When written to a logic 1, this bit enables the Signal Degrade (SD) Interrupt.
When written to a logic 1, this bit enables a Loss of Cell Delineation Interrupt. When
enabled, the interrupt appears on the MInt* pin for the LOCD interrupt indication bit.
When written to a logic 1, this bit enables a HEC Error Detected Interrupt. When
enabled, the interrupt appears on the MInt* pin for the HECDet interrupt indication bit.
When written to a logic 1, this bit enables a HEC Error Corrected Interrupt. When
enabled, the interrupt appears on the MInt* pin for the HECCorr interrupt indication
bit.
Reserved, set to 0.
When written to a logic 1, this bit enables a Cell Received Interrupt. When enabled, the
interrupt appears on the MInt* pin for the CellRcvd interrupt indication bit.
When written to a logic 1, this bit enables an Idle Cell Received Interrupt. When
enabled, the interrupt appears on the MInt* pin for the IdleRcvd interrupt indication
bit.
When written to a logic 1, this bit enables a Non-matching Cell Received Interrupt.
When enabled, the interrupt appears on the MInt* pin for the NonMatch interrupt
indication bit.
When written to a logic 1, this bit enables a Non-0 GFC Received Interrupt. When
enabled, the interrupt appears on the MInt* pin for the NonZerGFC interrupt indication
bit.
Mindspeed Technologies
Description
Description
™
4.0 Registers
4.1 Registers
4-21