cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 126

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

4.0 Registers
4.1 Registers
0x30—IDLMSK1 (Receive Idle Cell Mask Control Register 1)
The IDLMSK1 register contains the first byte of the Receive Idle Cell Mask. It modifies the ATM cell screen in
the RXIDL1 register. Setting a bit in the Mask register causes the corresponding bit in the received ATM idle
cell header to be disregarded for screening. For example, setting IDLMSK1, bit 0 to 1, causes cells to be
accepted as ATM idle cells with either 1 or 0 in the octet 1, bit 0 position. This header consists of 32 bits divided
among four registers.
0x31—IDLMSK2 (Receive Idle Cell Mask Control Register 2)
The IDLMSK2 register contains the second byte of the Receive Idle Cell Mask. It modifies the ATM cell screen
in the RXIDL1 register. Setting a bit in the Mask register causes the corresponding bit in the received ATM idle
cell header to be disregarded for screening. For example, setting IDLMSK1, bit 0 to 1, causes cells to be
accepted as ATM idle cells with either 1 or 0 in the octet 1, bit 0 position. This header consists of 32 bits divided
among four registers.
4-28
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IdlMsk2[7]
IdlMsk2[6]
IdlMsk2[5]
IdlMsk2[4]
IdlMsk2[3]
IdlMsk2[2]
IdlMsk2[1]
IdlMsk2[0]
IdlMsk1[7]
IdlMsk1[6]
IdlMsk1[5]
IdlMsk1[4]
IdlMsk1[3]
IdlMsk1[2]
IdlMsk1[1]
IdlMsk1[0]
Name
Name
Mindspeed Technologies
These bits hold the Receive Idle cell header mask for Octet 1 of the incoming cell.
These bits hold the Receive Idle cell header mask for Octet 2 of the incoming cell.
™
Description
Description
ATM Physical Interface (PHY) Devices
28250-DSH-002-C
CX28250