cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 83
cx28250
Manufacturer Part Number
cx28250
Description
Cx28250 Atm Physical Interface Phy Devices
Manufacturer
Mindspeed Technologies
Datasheet
1.CX28250.pdf
(213 pages)
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CX28250
ATM Physical Interface (PHY) Devices
Table 2-19. Interrupt Suppression during Error Conditions (2 of 2)
28250-DSH-002-C
NOTE(S):
(1)
(2)
(3)
Suppressed when RDI-P equals 110 or 101.
This is not suppressed in the CX28250-23 version.
This is not suppressed in the CX28250-26 version.
2.6.5.3 Interrupt
LOCD
HECDet
HECCorr
CellRcvd
IdleRcvd
NonMatch
NonZerGFC
Interrupts
Servicing
LOS
3
When an interrupt occurs on the MInt* pin, it could have been generated by any
of 35 events. The CX28250’s interrupt indication process ensures that a
maximum of two register reads are necessary to determine the source of an
interrupt. The interrupt is traced back to its source using the following steps:
ALL bits in that register are reset to their default values. Therefore, interrupt
service routines must be designed to handle multiple interrupts in the same
registers. In Level 2, OneSecInt is cleared when the register is read. However, the
summary bits are cleared only when the corresponding Level 1 register is read
and cleared.
LOF
3
1.
2.
All Level 1 bits are cleared when the register is read. Once the register is read,
Read the SUMINT register to see which bit(s) shows an interrupt.
– Bit 0, TxCellInt, reflects activity in the TXCELLINT register.
– Bit 1, RxCellInt, reflects activity in the RXCELLINT register.
– Bit 2, APSInt, reflects activity in the APSINT register.
– Bit 3 is reserved.
– Bit 4, OneSecInt, indicates a one-second interrupt.
– Bit 5, PthInt, reflects activity in the PTHINT register.
– Bit 6, LinInt, reflects activity in the LININT register.
– Bit 7, SecInt, reflects activity in the SECINT register.
If necessary, read the appropriate TXCELLINT, RXCELLINT, APSINT,
PTHINT, LININT, or SECINT register.
OOF
3
Mindspeed Technologies
AIS-L
3
AIS-P
3
Suppressed during:
LOP-P
3
™
RDI-P
RDI-L
2.0 Functional Description
2.6 Microprocessor Interface
Uneq-P
3
LOCD
3
3
3
3
3
3
2-47
(2)
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