cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 67

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cx28250

Manufacturer Part Number
cx28250
Description
Cx28250 Atm Physical Interface Phy Devices
Manufacturer
Mindspeed Technologies
Datasheet

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CX28250
ATM Physical Interface (PHY) Devices
Figure 2-11. Cell Delineation Process
Figure 2-12. Header Error Check Process
28250-DSH-002-C
Errors Detected
(Drop Cell)
Hunt
Detection
Mode
the HEC is valid. If a single-bit error in the header is detected, the error is
corrected, optionally, and the cell is passed to the ATM block. If HEC checking is
enabled and HEC correcting is disabled (bit 3 in the CVAL register [0x08]), cells
with single-bit HEC errors are discarded. If a multi-bit error is detected, the cell is
dropped. Once either type of error is noted, all subsequent errored cells are
dropped until a valid cell is received. This rule applies even for single-bit errors
that could be corrected. Once a valid cell is detected, the process begins again.
(See
When in the sync state of cell delineation, cells are passed to the ATM block if
1 Correct HEC
Figure
Header Error Processing in Sync State
Apparent Multi-bit Error
Mindspeed Technologies
2-12.)
7 Errored HECs
1 Errored HEC
(Drop Cell)
No Errors Detected
(Correct Error and Pass Cell)
(Pass Cell)
Apparent Single-bit Error
Pre-Sync
6 Correct HECs
Sync
Correction
Mode
No Errors Detected
(Pass Cell)
2.0 Functional Description
500035_013
2.4 ATM Cell Processor
500035_014
2-31

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