cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 72

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

2.0 Functional Description
2.5 UTOPIA Interface
2.5.2 UTOPIA 8-bit and 16-bit Bus Widths
2-36
The CX28250 has two bus width options, 8-bit or 16-bit, which are selected in bit
3 of the UTOP1 register (0x0A). The protocols and timing are the same in both
modes except that 8-bit mode uses only the lower half of the data bus
(TxData[7:0] and RxData[7:0]).
by the UBusWidth pin (for the CX28250-26 only). Refer to
description of this pin.
bytes are used for header information. The remaining bytes are used for payload.
Table 2-16. Cell Format for 8-bit Mode
bytes contain header information. The sixth byte, UDF2, is required to maintain
alignment but is not read by the CX28250. The remaining bytes are used for
payload.
Table 2-17. Cell Format for 16-bit Mode
NOTE:
Bit 15
Bit 7
Note that the power-on default value for the UTOP1 register bit 3 is controlled
In 8-bit mode, each ATM cell consists of 53 bytes (see
In 16-bit mode, the cells consists of 54 bytes (see
Normally, the HEC is calculated by the PHY and put in byte 5, UDF1.
However, setting bit 7 of the CGEN register (0x04) to 1 disables HEC
calculation. In this case, data inserted by the ATM layer into byte 5 is
transmitted by the PHY.
Mindspeed Technologies
UDF1 (HEC) (byte 5)
UDF1 (HEC) (byte 5)
Payload 48
Payload 47
Payload 1
Header 1
Header 2
Header 3
Header 4
Payload 1
Header 1
Header 3
...
...
Bit 0
Bit 8
Bit7
UDF2 (User definable, see UDF2, 0x74)
™
ATM Physical Interface (PHY) Devices
Payload 48
Payload 2
Table
Header 2
Header 4
...
Table
2-17). The first 5
Table 1-1
28250-DSH-002-C
2-16). The first 5
for a
Bit 0
CX28250