cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 77

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

CX28250
ATM Physical Interface (PHY) Devices
2.6.2 Status and Control
2.6.3 Counters
28250-DSH-002-C
Several registers provide status and control information to the microprocessor.
Status information includes interrupts, counters, and generic functional status.
Control information includes configuration and real-time control, according to
the specific function of each control register. There are two types of status input:
live and latched. Live status provides the current status of the device. Latched
status is used for rapidly changing states to capture information until it can be
read.
master reset, output status, and device part number and revision. The
software-controlled Master Reset, GEN register (0x00) bit 0, restarts all device
functions and sets the control and status registers to their default values. The
OUTSTAT register (0x02) provides a means for controlling external devices via
the OutStat pins (1-5 and 126-128). It is enabled by setting the StatPinMode (bit
2) of the GEN register (0x00). The VER register (0x03) uniquely identifies the
device and revision level.
The CX28250 counters record events within the device. There are two types of
events: error events, such as Section BIP errors, and transmission events, such as
transmitted ATM cells.
reading the least significant byte first. This guarantees that the value contained in
each component register accurately reflects the composite counter value at the
time the least significant byte was read since the counter may be updated while
the component registers are being read.
that may occur within a one-second interval. The counters are cleared after being
read. Therefore, if the counters are read every second, the application receives an
accurate recording of all event occurrences.
This device contains general purpose status and control functions, such as a
Counters which are comprised of more than one register must be accessed by
Each counter is large enough to accommodate the maximum number of events
Mindspeed Technologies
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2.0 Functional Description
2.6 Microprocessor Interface
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