cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 65

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

CX28250
ATM Physical Interface (PHY) Devices
2.4.1 ATM Cell Transmitter
28250-DSH-002-C
2.4 ATM Cell Processor
The CX28250 ATM cell processor block is responsible for recovering cell
alignment using the HEC octet, performing header error correction, and
descrambling the payload octets. The resulting ATM cells are then passed to the
ATM layer via the UTOPIA interface. Simultaneously, the ATM block is
receiving data from the ATM layer, optionally calculating the HEC, formatting
the 48-octet payload segments into 53-octet ATM cells, and sending the cells to
the SONET block. If no data is being received from the ATM layer, the cell
processor generates idle cells based on the data programmed into the associated
registers.
and performs the payload CRC calculations as required by the AAL formats. It
generates cell status bits, cell counts, and error counts.
The ATM cell transmitter controls the generation and formatting of 53-octet ATM
cells that are sent to the Framer block. The ATM transmitter block formats an
octet stream containing ATM data cells from the ATM layer device when such
cells are available. All 53 octets of the data cells can be obtained from the external
data source and formatted into the outgoing octet stream.
The calculated HEC octet can be inserted in place of the incoming data octet by
writing DisHEC (bit 7) in the CGEN register (0x04) to a logic 0. For testing
purposes, this HEC octet can be corrupted by XORing the calculated value with a
specific error pattern input set in the ERRPAT register (0x07). This HEC error is
achieved by writing InsHECErr (bit 1) in the ERRINS register (0x06) to a logic 1.
The remaining 48-octet payload field of the outgoing cell is obtained from the
external data source. The payload is normally scrambled. This can be disabled by
setting bit 2 of the TXSEC register.
automatically in the outgoing data stream unless bit 0 of TXCELL is set to 1. The
payload of these cells is read from the Transmit Idle Cell Payload Control register,
IDLPAY (0x05). The 4-octet header field for these idle cells comes from the
TXIDL1-4 registers (0x20-23). The HEC octet is calculated and inserted
automatically. The payload field is filled with the octet contained in the IDLPAY
register (0x05).
from the ATM layer device. Header patterns can be modified in the TXHDR1-4
registers (0x1C - 0x1F) and inserted into outgoing cells in place of header bytes
received from the ATM layer. Bits 0-4 in the CGEN register (0x04) control
whether the original header cells or the replacement cells are sent.
The CX28250 has all the counters necessary for capturing ATM error events
This block calculates the HEC octet in the outgoing cell from the header field.
When no data is coming from the ATM layer, the CX28250 inserts idle cells
In normal operation, the 4-octet header field in the outgoing cell is passed on
Mindspeed Technologies
™
2.0 Functional Description
2.4 ATM Cell Processor
2-29