cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 86

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

2.0 Functional Description
2.7 Loopback Modes
2.7.3 Source Loopback
Figure 2-17. Source Loopback Diagram
2-50
PECL Logic
LRxData+/-
LTxClkO+/-
ATM WIRE
LTxData+/-
Interface
LTxClkI+/-
LRxClk+/-
SigDet
Level
(19.44 MHz)
PLLCLK
TCK
Line Interface
TRST*
and Clock
Interface
Recovery
Controller
Transmit
Receive
Line
JTAG
8kHzIn
Loopback
TMS
Control
TDI
TDO
TxDL
Source loopback is enabled and disabled by bit 2 the CLKREC register (0x01).
When source loopback is enabled, all data transmitted by the CX28250 is also
looped back through the Receive Line Interface. Data from the PMD is ignored.
Tx Overhead
Rx Overhead
SONET Line Framer
Extract
Insert
Transmit Framer
Receive Framer
STS-3c/STM-1
STS-3c/STM-1
Mindspeed Technologies
StatOut[0:7]
Status
InsPthAIS
ATM Cell Framer
InsLnAIS
Performance Monitoring
Receive Cell
MRdy
Alignment
Interrupt Control
Cell Counters
OneSecIn
Generation
Clock and
OneSecOut
Tx Cell
Control
MInt*
™
RxFrameRef
Rx VPI/VCI
Screening
Validation
ATM Physical Interface (PHY) Devices
MAddr[6:0]
Rx Cell
TxFrameRef
Microprocessor
MData[7:0]
Interface
PFOut
Interface
Interface
Transmit
UTOPIA
Receive
UTOPIA
Level 2
Level 2
4-cell
4-cell
FIFO
FIFO
Control Lines
Host
Host
28250-DSH-002-C
LFOut
Interface
UTOPIA
Level 2
UTxClk
UTxClAv
UTxEnb*
UTxSOC
UTxData[15:0]
TxPrty
UTxAddr[4:0]
URxClk
URxClAv
URxEnb*
URxSOC
URxData[15:0]
URxPrty
URxAddr[4:0]
CX28250
500035_020