cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 29

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

CX28250
ATM Physical Interface (PHY) Devices
Table 1-1. CX28250 Pin Definitions (7 of 12)
28250-DSH-002-C
StatOut[7]
StatOut[6]
StatOut[5]
StatOut[4]
StatOut[3]
StatOut[2]
StatOut[1]
StatOut[0]
TxDL
Pin Label
Status Outputs[7:0]
Transmit Data Link
Input
Signal Name
Mindspeed Technologies
No.
A4
C4
B4
A3
C3
B3
A2
B2
P3
Type
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
I/O
O
O
O
O
O
O
O
O
I
This pin reflects either the value in bit 7 of the
OUTSTAT register (0x41) or LOS, as selected by bit 2
of register GEN (0x00). If selected by bit 0 or 1 of
RXLIN (0x46), this pin will be the D1-D3 or D4-D12
receive data link serial clock output.
This pin reflects either the value in bit 6 of the
OUTSTAT register (0x41) or OOF, as selected by bit 2
of register GEN (0x00). If selected by bit 0 or 1 of
RXLIN (0x46), this pin will be the D1-D3 or D4-D12
receive data link serial data output.
This pin reflects either the value in bit 5 of the
OUTSTAT register (0x41) or LOP, as selected by bit 2
of register GEN (0x00). If selected by bit 0 or 1 of
RXLIN (0x46), this pin will be the D1-D3 or D4-D12
receive data link indication output. This output is high
during the time that clock/data outputs contain pulses
for D1-D3 octets. It is low during the time that
clock/data outputs contain pulses for D4-D12 octets.
This pin reflects either the value in bit 4 of the
OUTSTAT register (0x41) or AIS-L, as selected by bit
2 of register GEN (0x00). If selected by bit 4 of TXLIN
(0x0D) or bit 6 of TXSEC (0x0C), this pin will be the
D1-D3 or D4-D12 transmit data link serial clock
output.
This pin reflects either the value in bit 3 of the
OUTSTAT register (0x41) or RDI-L, as selected by bit
2 of register GEN (0x00). If selected by bit 4 of TXLIN
(0x0D) or bit 6 of TXSEC (0x0C), this pin will be the
D1-D3 or D4-D12 transmit data link indication output.
This output is high during the time that clock/data
inputs are expected for D1-D3 octets, and low for
D4-D12.
This pin reflects either the value in bit 2 of the
OUTSTAT register (0x41) or AIS-P, as selected by bit
2 of register GEN (0x00). If selected by bit 4 of TXLIN
(0x0D) or bit 6 of TXSEC (0x0C), this pin will output a
pulse at the beginning of every cell slot time (both
idle and data cells), synchronized to the UTOPIA
transmit side.
This pin reflects either the value in bit 1 of the
OUTSTAT register (0x41) or RDI-P, as selected by bit
2 of register GEN (0x00).
This pin reflects either the value in bit 0 of the
OUTSTAT register (0x41) or LOCD, as selected by bit
2 of register GEN (0x00).
This pin is used to serially transmit data over the
D1-D3 and D4-D12 data link.
™
1.4 CX28250 Pinout and Pin Descriptions
Description
1.0 Product Description
1-13