cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 42

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

2.0 Functional Description
2.1 Line Interface
2.1.2 Signal Detect Interface
2-6
The LSigDet pin on the CX28250 indicates when the PMD has lost its signal. If
the LSigDet goes low, the CX28250 internally forces its receive data to logic ‘0’
to prevent false framing indications. Designs that don’t use the LSigDet input
must tie this pin high and then ensure that they either externally force the receive
data to a logic ‘0’ or detect false framing/cell delineation indications with
software.
connected directly to a TTL interface without external components. When using a
single-ended PECL interface, a standard PECL termination of 50 Ω to V
is required for most PMDs. The PECL termination can be implemented by using
the Thevenin equivalent circuit shown in
Figure 2-4. Single-ended PECL Diagram
Note:
The LSigDet pin can be driven by TTL or PECL drivers. The CX28250 can be
The termination network shown is valid for a 3.3 V PMD. For a 5.0 V PMD, please refer
to Figure 3-4.
3.3 V
Signal Detect
(SD)
Mindspeed Technologies
PMD
+3.3 V
R
R
1
2
= 130 Ω
= 82 Ω
™
Figure
LSigDet
ATM Physical Interface (PHY) Devices
2-4.
Vsref
3.3 V
–
+
CX28250
28250-DSH-002-C
Internal
logic
CX28250
cc
500035_008
– 2 V