cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 121

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

CX28250
ATM Physical Interface (PHY) Devices
0x36—ENLIN (Receive Line Interrupt Mask Control Register)
The ENLIN register controls which of the interrupts listed in the LinInt register (0x3E) appear on the MInt* pin,
provided that EnLinInt (bit 6) in the ENSUMINT register (0x34) is enabled, and EnIntPin (bit 6) in the GEN
register (0x00) is enabled.
0x6F—ENPFOUT (Enable Path Fail Output)
This register controls which events will cause the PFOut pin to be asserted:
28250-DSH-002-C
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
EnS1Intr
EnAIS-L
EnRDI-L
EnB2Err
EnK1K2
EnLOP
Name
REI-L
ZInt
Name
LOP-P
AIS-L
AIS-P
LOCD
LOS
OOF
LOL
LOF
When written to a logic 1, this bit enables the LOP Interrupt.
When written to a logic 1, this bit enables the K1K2 Interrupt.
When written to a logic 1, this bit enables the AIS-L Interrupt.
When written to a logic 1, this bit enables the RDI-L Interrupt.
When written to a logic 1, this bit enables the B2 Error Interrupt.
When written to a logic 1, this bit enables the REI-L Error Interrupt.
When written to a logic 1, this bit enables the Z0
When written to a logic 1, this bit enables the S1 Byte Change Interrupt.
When enabled, assertion of LOS status bit will cause the PFOut pin to be asserted.
When enabled, assertion of LOL status bit will cause the PFOut pin to be asserted.
When enabled, assertion of OOF status bit will cause the PFOut pin to be asserted.
When enabled, assertion of LOF status bit will cause the PFOut pin to be asserted.
When enabled, assertion of AIS-L status bit will cause the PFOut pin to be asserted.
When enabled, assertion of AIS-P status bit will cause the PFOut pin to be asserted.
When enabled, assertion of LOP-P status bit will cause the PFOut pin to be asserted.
When enabled, assertion of LOCD status bit will cause the PFOut pin to be asserted.
Mindspeed Technologies
Description
Description
™
1
, Z0
2
, or Z2 interrupts.
4.0 Registers
4.1 Registers
4-23