cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 4

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

SONET Framer Functions
• Recovers frame location using F6/28 framing pattern
• Processes pointer to locate payload envelope
• Provides Out-of-Frame (OOF), Loss-of-Pointer (LOP), and
• Provides frame and payload position information to other
• Generates clocks and frame counters
• Maps cell data into payload envelope
• Generates all section, line, and path overhead and alarms
• Performs cell and frame scrambling before transmission
• Detects and integrates alarms for reporting in status
• Detects BIP and Remote Error Indication (REI) errors for
• Recovers D1-D3 and D4-D12 data link
Cell Alignment Framing Section
• Recovers cell alignment from HEC
• Performs HEC error correction
• Strobes and cell sync for UTOPIA interface
• Generates cell status bits, cell counts, and error counts
• Reads cell data from the UTOPIA FIFO
• Inserts headers and generates HEC
• Inserts idle cells when no traffic is ready
Microprocessor Interface
• SRAM-like interface mode with high-performance or
• Glueless CX2823x SAR interface mode
• 8-bit data bus
• Open-drain interrupt output
The following diagram is a Network Interface Card (NIC) application of the CX28250
28250-DSH-002-C
Alarm Indication Status (AIS) status
blocks
registers
error counters
low-power access selection
Note(s):
1. The CX28234 SAR has an 8 bit UTOPIA level 1 interface.
2. The CX28236 SAR has a 8/16 bit UTOPIA level 1/2 interface and supports multi-PHY operation.
Bus
PCI
PCI
Interface
CX28234/CX28236
UTOPIA Bus
Local Bus
Interface
Interface
Mindspeed Technologies
UTOPIA Bus
Local Bus
SRAM
Support for Automatic Protection Switching (APS)
• APS driver source code available from Mindspeed.
• Register control allows for support of APS
• Software support:
• K1/K2 Transmit control register allows transmission of any
• Separate control bits for AIS, line REI
• K1/K2 receive status register allows observation of incoming
• Maskable interrupt on any change in received value
• Software interrupt routine can easily implement APS
• Signal Fail/Signal Detect BER threshold monitoring
• Line Fail and Path Fail hardware outputs
• Line AIS and Path AIS can be generated by hardware input
Counters/Status and Interrupt Registers
• Summary interrupt indications
• Configuration of interrupt enables
• One-second status latching
• One-second counter latching
• Eight general purpose outputs, configurable as status
– CX28297 Device Driver
– CX28299 APS Driver
value
octet values
protocol
indicator pins
pins
Microprocessor
Interface
UTOPIA
Interface
™
CX28250
Interface
PMD
Fiber
or
Cat 5
500035_002