cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 177

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cx28250

Manufacturer Part Number
cx28250
Description
Cx28250 Atm Physical Interface Phy Devices
Manufacturer
Mindspeed Technologies
Datasheet

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CX28250
ATM Physical Interface (PHY) Devices
Table 5-4. Asynchronous Mode, Read Timing Table (High-Performance Access Time)
28250-DSH-002-C
Label
t
t
t
t
t
t
t
t
t
NOTE(S):
(1)
(2)
(3)
pwl
pwh
s
h
en
pd
dis
enzl
dislz
Due to internal sampling mechanisms used, these times are specified in clock cycles rather than absolute values. For these
calculations Clk equals the period of clock selected via the Clk pin (either 26 ns or 52 ns; see
Timing starts with either MCs* or MRd*, whichever occurs last.
When reading from internal Trace buffers, t
Pulse Width Low, (MCs* + MRd*)
Pulse Width High, (MCs* +MRd*)
Setup, MAddr[6:0] to the falling edge of (MCs* + MRd*)
Hold, MAddr[6:0] from the rising edge of (MCs* + MRd*)
Enable, MData[7:0] from the falling edge of (MCs* + MRd*)
Propagation Delay, MData[7:0] from the falling edge of (MCs* +
MRd*)
Disable, MData[7:0] from the rising edge of (MCs* + MRd*)
Enable, MRdy from the falling edge of (MCs* + MRd*)
Disable, MRdy from the rising edge of (MCs* + MRd*)
Description
Mindspeed Technologies
(2)
pd
= 19.7 ns.
5.0 Electrical and Mechanical Specifications
2 x Clk + 15 ns
Clk + 15 ns
2 x Clk +1
Min
2
7
2
2
1
(1)
(1)
Section
2* Clk + 10
5.1 Timing Specifications
2.6).
3 x Clk +10
Max
13
13
10
(1)(3)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
5-11

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