cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 21

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

CX28250
ATM Physical Interface (PHY) Devices
Figure 1-2. CX28250 Logic Diagram
28250-DSH-002-C
UTOPIA Transmit Start-Of-Cell
Address Strobe,Write Control
UTOPIA Transmit Parity Input
Receive PLL Filter Neg. Input
Receive PLL Filter Pos. Input
Write/Read~,Read Control
UTOPIA Transmit Address
UTOPIA Receive Address
Sync/Async Mode Select
UTOPIA Transmit Enable
One-Second Clock Sync
Transmit Data Link Input
UTOPIA Receive Enable
Phase Lock Loop Clock
UTOPIA Transmit Clock
UTOPIA Receive Clock
UTOPIA Transmit Data
8 kHz Ref. Clock Input
Transmit Clock Input
Receive Clock Input
Receive Data Input
Test Mode Select
Signal Detection
Processor Clock
Insert Path AIS
Insert Line AIS
Test Data Input
Address Bus
Chip Select
Test Reset
Test Clock
Reset
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
InsPthAIS
InsLnAIS
OneSecIn
8kHzIn
Reset
MClk, MAcsSel
TRST*
TCK
TMS
TDI
LSigDet
LPLLClk
LTxClkI+/-
LRxData+/-
LRxClk+/-
MSyncMode
LRxPFN
LRxPFP
MAs*, MWr*
MW/R*, MRd*
MCs*
MAddr[6:0]
UTxEnb*
UTxAddr[4:0]
UTxData[15:0]
URxClk
URxEnb*
URxAddr[4:0]
TxDL
UTxClk
UTxSOC
UTxPrty
Mindspeed Technologies
I = Input, O = Output
Clock and Control
Microprocessor
PMD Line
Interface
Transmit
Data Link
UTOPIA
Receive
Interface
UTOPIA
Status
JTAG
URxData[15:0]
StatOut[7:0]
RxFrameRef
TxFrameRef
MData[7:0]
OneSecOut
LTxClkO+/-
LTxData+/-
UTxClAv
URxSOC
URxClAv
URxPrty
LTxPFN
LTxPFP
PFOut
LFOut
MRdy
MInt*
TDO
™
O
O
O
O
O
O
O
I/O
O Status Output
O
O
O
O
O UTOPIA Receive Data Bus
O Transmit PLL Filter Pos. Output
O Transmit PLL Filter Neg. Output
O
O
O Microprocessor Ready
Line Fail Output
Path Fail Clock
One-Second Output
8 kHz Transmit Frame Clock
8 kHz Receive Frame Clock
Transmit Clock Output
Transmit Data Output
UTOPIA Receive Cell Available
UTOPIA Receive Start of Cell
UTOPIA Receive Parity
UTOPIA Transmit Cell Available
Microprocessor Interrupt
Processor Data Bus
Test Data Output
1.0 Product Description
1.3 Logic Diagram
500035_003
1-5