cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 35

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

CX28250
ATM Physical Interface (PHY) Devices
Figure 1-4. CX28250 Detailed Block Diagram
28250-DSH-002-C
PECL Logic
LRxData+/-
ATM WIRE
LTxClkO+/-
LTxData+/-
Interface
LTxClkI+/-
LRxClk+/-
SigDet
Level
(19.44 MHz)
PLLCLK
TCK
Line Interface
TRST*
and Clock
Recovery
Controller
Transmit
Interface
Receive
JTAG
Line
TMS
Loopback
Control
TDI
TDO
TxDL
1.5 Block Diagram and Descriptions
Figure 1-4
transmitted from the host system, octet-wide or 16-bit data enters the CX28250
via the UTOPIA port. The CX28250 assembles the host data into ATM cells and
formats it for serial-line transmission by the SONET line framer.
into octets and passes it to the ATM cell processing block. Octet data is then
aligned into ATM cells, checked, and sent to the UTOPIA port.
transmission. Also included are overhead interfaces, data links, and event
counters.
block. It generates cells for transmission and validates received cells. Included are
HEC generators and detectors, data scramblers, and counters.
It controls transmit priority and rate, and has counters for events and errors.
Tx Overhead
Rx Overhead
SONET Line Framer
In the receive direction, the SONET line framer frames serial network data
The line framer block connects to external interfaces for data reception and
The HEC ATM cell alignment block accepts octet data from the line framer
The UTOPIA interface communicates with the next layer of ATM processing.
Extract
Insert
Transmit Framer
Receive Framer
STS-3c/STM-1
STS-3c/STM-1
Mindspeed Technologies
is a detailed block diagram of the CX28250. When traffic is
8kHzIn
StatOut[0:7]
Status
InsPthAIS
ATM Cell Framer
InsLnAIS
Performance Monitoring
Receive Cell
Alignment
Interrupt Control
Cell Counters
OneSecIn
Generation
Clock and
OneSecOut
Tx Cell
Control
MInt*
™
RxFrameRef
Rx VPI/VCI
Screening
Validation
MAddr[6:0]
Rx Cell
MRdy
TxFrameRef
1.5 Block Diagram and Descriptions
Microprocessor
MData[7:0]
Interface
PFOut
Interface
Interface
1.0 Product Description
Transmit
UTOPIA
Receive
UTOPIA
Level 2
Level 2
4-cell
4-cell
FIFO
FIFO
Control Lines
Host
Host
LFOut
Interface
UTOPIA
Level 2
UTxClk
UTxClAv
UTxEnb*
UTxSOC
UTxData[15:0]
TxPrty
UTxAddr[4:0]
URxClk
URxClAv
URxEnb*
URxSOC
URxData[15:0]
URxPrty
URxAddr[4:0]
500035_005
1-19