cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 152

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

4.0 Registers
4.1 Registers
0x40—TXCELLINT (Transmit Cell Interrupt Indication Status Register)
The TXCELLINT register indicates that a change of status has occurred within its affiliated status signals.
0x62—TXCNTH (Transmitted Cell Counter [High Byte])
The TXCNTH counter tracks the number of transmitted cells.
4-54
NOTE(S):
(1)
Bit
Bit
Single event—A 0–> 1 transition on the corresponding status bit causes this interrupt to occur provided that this interrupt has
been enabled by the corresponding enable bit. Reading the interrupt register clears the interrupt.
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
CellSentInt
SOCErrInt
ParErrInt
TxOvflInt
RxOvflInt
TxCnt[18]
TxCnt[17]
TxCnt[16]
Name
Name
—
—
—
—
—
—
—
—
(1)
(1)
(1)
(1)
(1)
Reserved, set to 0.
Reserved, set to 0.
Reserved, set to 0.
Reserved, set to 0.
Reserved, set to 0.
Transmitted cell counter bit 18 (MSB).
Transmitted cell counter bit 17.
Transmitted cell counter bit 16.
When a logic 1 is read, this bit indicates that a Parity Error has occurred.
When a logic 1 is read, this bit indicates that a Start of Cell Alignment Error has
occurred.
When a logic 1 is read, this bit indicates that a Transmit FIFO Overflow has occurred.
When a logic 1 is read, this bit indicates that a Receive FIFO Overflow has occurred.
When a logic 1 is read, this bit indicates that a Cell Sent Interrupt has occurred.
Reserved, set to 0.
Reserved, set to 0.
Reserved, set to 0.
Mindspeed Technologies
Description
Description
™
ATM Physical Interface (PHY) Devices
28250-DSH-002-C
CX28250